Table Of ContentVERILOG® QUICKSTART
VERILOG® QUICKSTART
by
James M. Lee
Cadence Design Systems, Inc.
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"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
ISBN 978-1-4613-7801-3 ISBN 978-1-4615-6113-2 (eBook)
DOI 10.1007/978-1-4615-6113-2
Additional material to this book can be downloaded from http://extras.springer.com
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright © 1997 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1995
Softcover reprint of the hardcover 1st edition 1995
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
TABLE OF CONTENTS
LIST OF FIGURES xii
LIST OF EXAMPLES xiv
LIST OF TABLES xix
1 INTRODUCTION 1
Framing Verilog Concepts 3
The Design Abstraction Hierarchy 3
Types of Simulation 4
Types of Languages 4
Simulation versus Programming 5
HDL Learning Paradigms 5
Where To Get More Information 7
Reference Manuals 8
Usenet 8
Talk Verilog 8
2 INTRODUCTION TO THE VERI LOG LANGUAGE 9
Identifiers 9
Escaped Identifiers 10
White Space 11
Comments 12
Numbers 12
Text Macros 13
Modules 14
Semicolons 14
Value Set 15
Strengths 15
Numbers, Values, and Unknowns 16
vi Verilog Quickstart
3 STRUCTURAL MODEUNG 19
Primitives 19
Ports 20
Ports in Primitives 20
Ports in Modules 21
Instances 21
Hierarchy 22
Hierarchical Names 24
Top-Level Modules 26
You Are Now Ready To Run Your First Simulations 26
Exercise 1 The Hello Simulation 26
Exercise 2 The 8-Bit Hierarchical Adder 27
4 BEHAVIORAL MODEUNG 31
Starting Places for Places for Blocks of Behavioral Code 32
The initial Keyword 32
The always Keyword 32
Delays 33
begin-end Blocks 34
fork-join Blocks 37
System Tasks for Printing Out Results 45
What Is a System Task? 45
$display and Its Relatives 45
Other Commands To Print Results 47
Writing to Files 48
Setting the Default Radix 50
Exercise 3 Printing Out Results from Wires Buried in the Hierarchy 51
Special Characters 51
Suppressing Spaces in Your Output 52
Data Objects in Verilog 55
Nets 55
Ranges 56
Implicit Nets 57
Registers 58
Memories 58
Integers and Reals 59
Time 60
Parameters 60
Events 61
Strings 61
Procedural Assignments 62
Ports and Registers 66
vii
5 OPERATORS 69
Binary Operators 69
Unary Operators 71
Reduction Operators 72
Ternary Operator 73
Equality Operators 74
Concatenations 77
Logical versus Bit-wise Operations 78
Operations That Are Not Legal on Reals 80
Working with Strings 80
Combining Operators 81
Sizing Expressions 81
6 WORKING WITH BEHAVIORAL MODELING 83
Continuous Assignment 83
Event Control 87
The if Statement 92
The case Statement 93
Exercise 4 Using Expressions and case 96
Loops 102
The forever Loop 102
The repeat Loop 103
The while Loop 104
The for Loop 105
Procedural Continuous Assignments 106
tasks 111
functions 117
Exercise 5 Functions and Continuous Assignments 120
A Reminder about Ports and Registers 120
Modeling with inout Ports 120
Named Blocks 121
The disable Statement 122
When is a Simulation Done? 124
7 USER-DEFINED PRIMITIVES 127
Combinatorial UDPs 128
Optimistic Mux 128
Pessimistic Mux 128
The Gritty Details 129
Sequential UDPs 130
UDP Instances 133
The Final Details 133
Exercise 6 Using UDPs 134
viii Verilog Quickstart
8 PARAMETERIZED MODULES 137
n-Bit Mux 138
n-Bit Adder 138
nBymMux 139
nBymRam 140
Using Parameterized Modules 141
9 STATE MACHINES 143
State Machine Types 143
State Machine Modeling Style 145
State Encoding Methods 153
Default Conditions 155
Implicit State Machines 156
Registered and Unregistered Outputs 157
Factors in Choosing a State Machine Modeling Style 158
10 MODELING TIPS 159
Modeling Combinatorial Logic 159
Combinatorial Models Using Continuous Assignments 160
Combinatorial Models Using the always Block and regs 161
Combinatorial Models Using Functions 164
Modeling Sequential Logic 165
Sequential Models Using always 165
Sequential Models Using initial 165
Sequential Models Using tasks 168
Modeling Asynchronous Circuits 170
Modeling a One-Shot 170
Modeling Asynchronous Systems 171
Special-Purpose Models 177
Two-Dimensional Arrays 177
Z-Detectors 178
Multiplier Examples 179
A Proven, Successful Approach to Modeling 189
11 MODELING STYLE TRADE-OFFS 191
Forces That Influence Modeling Style 191
Evolution of a Model 192
Modeling Style and Synthesis 193
Is It Synthesizable? 194
Learning From Other People's Mistakes 195
When To Use UDPs 202
ix
12 TEST BENCHES AND TEST MANAGEMENT 203
Introduction to Testing 203
Model Size versus Test Volume 204
Functional Testing 205
Regression Testing 205
Self-Checking Test Benches 205
Sign-Off 210
System Test versus Unit Tests 210
Response-Driven Stimulus 211
Test Benches for Inouts 214
Loading Files into Verilog Memories 215
Test Benches with No Test Vectors 219
Using a Script To Run Test Cases 219
Modeling BIST 220
The Surround and Capture Method 222
13 COMMON ERRORS 227
Mismatched Ports 227
Missing or Incorrect Declarations 228
Missing Registers 228
Missing Widths 229
Reversed Ranges 230
Improper Use of Procedural Continuous Assignments 230
Missing initial or always Blocks 231
Zero-Delay always Loops 231
initial Instead of always 232
Missing Initialization 232
Overly Complex Code 233
Unintended Storage 233
Timing Errors 233
Negative Setup Time 234
Zero-Delay Races 234
14 DEBUGGING A DESIGN 237
Overview of Functional Debugging 237
Where Are the Errors? 238
Universal Techniques 238
Printing Out Messages 238
"I am here." 238
Values 239
The Log File 240
Using Wavefonns 240
Interactive Debugging 241
Going Interactive 241
x Verilog Quickstart
The Prompts 242
Special Keys in Interactive Mode 244
Command History 249
The Key File 252
Traversing and Observing 257
Back-Tracing Fan-In 261
Usingforce and release 262
Waveforms, Graphic User Interfaces, and Other Conveniences 263
Catching Problems Later in a Simulation 263
Isolating Differences in Models 265
Summary of Debugging 266
Appendix A GATE LEVEL DETAILS 269
Primitive Descriptions 269
Logic Gates 269
AJNIT) 269
NAJNIT) 270
OR 271
NOR 271
XOR 272
XNOR 272
Buffe~ 273
BUF 273
NOT 273
BUFIFO 274
BUFIFI 274
NOTIFO 275
NOTIFI 276
PULLDOWN 276
PULLUP 277
Switches 277
NMOS and RNMOS 278
PMOS and RPMOS 279
CMOS and RCMOS 280
TRAN and RTRAN 281
TRANIFO and RTRANIFO 281
TRANIFI and RTRANIFI 282
Instance Details 282
Delays 282
Delay Units 283
Printing Out Time and the Timescale 284
Strengths 284
Displaying strengths with %v 285
Strength reduction of switch primitives 286
xi
Appendix B EXAMPLE SUMMARY 287
INDEX 299
