Verilog-Mode Relieving the veri-tedium of Verilog

41 Pages·2009·2.25 MB·English

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9/25/2009
wsnyder
Verilog-Mode
Still Reducing the Veri-Tedium
http://www.veripool.org/papers
/*AUTOAUTHOR*/
Wilson Snyder
[email protected]
Last updated Sep, 2009
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9/25/2009
Agenda
wsnyder

The Tedium of Verilog
• What do I mean by Tedium?
• Why bother to reduce it?
• How do we reduce it?

Verilog-mode Features
• Wires, Regs, Null Modules, etc…
• Instantiations

Help and Support
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9/25/2009
Module Tedium? (1995)
wsnyder
Argument list is same as
mmoodduullee tteeddiiuumm ((ii11,,ii22,,oo11,,oo22));;
input/output statements.
iinnppuutt ii11,,ii22;;
oouuttppuutt oo11,,oo22;;
Regs needed for outputs.
rreegg oo11;;
wwiirree oo22;;
Wires needed for interconnections.
wwiirree iinntteerr11;;
aallwwaayyss @@((ii11 oorr ii22 oorr iinntteerr11))
oo11 == ii11 || ii22 || iinntteerr11;;
Sensitivity lists.
ssuubb ss11 ((..ii ((ii11)),,
..oo ((oo11)),,
Named based instantiations
..iinntteerr11 ((iinntteerr11))));;
mostly replicate input/outputs
ssuubb ss22 ((..ii ((ii22)),, from the sub module.
..oo ((oo22)),,
..iinntteerr11 ((iinntteerr11))));;
eennddmmoodduullee
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9/25/2009
Module Tedium? (2009)
wsnyder
mmoodduullee tteeddiiuumm ((
iinnppuutt ii11,, ii22,,
Regs still needed for outputs.
oouuttppuutt oo11,, oo22));;
( “output reg” somewhat better)
rreegg oo11;;
wwiirree oo22;;
Wires still needed for interconnections.
wwiirree iinntteerr11;;
aallwwaayyss @@**
@* - Proposed based on Verilog-Mode!
oo11 == ii11 || ii22 || iinntteerr11;;
ssuubb ss11 ((..ii ((ii11)),,
.* - Saves lots of typing,
..oo ((oo22)),,
But can’t see what’s being
..**));;
connected!
ssuubb ss22 ((..ii ((ii11)),,
..oo ((oo22)),,
When connections aren’t
..**));;
simple, you still need to make
eennddmmoodduullee
connections by hand
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9/25/2009
Why eliminate redundancy?
wsnyder
 Reduce spins on fixing lint or compiler warnings
 Reduce sensitivity problems
- If you forget (or don’t have) a linter, these are horrible to debug!
 Make it easier to name signals consistently
through the hierarchy
- Reduce cut & paste errors on multiple instantiations.
- Make it more obvious what a signal does.
 Reducing the number of lines is goodness alone.
- Less code to "look" at.
- Less time typing.
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9/25/2009
What would we like in a fix?
wsnyder
 Don’t want a new language
- All tools would need a upgrade!
- (SystemVerilog unfortunately faces this hurdle.)
 Don’t want a preprocessor
- Yet another tool to add to the flow!
- Would need all users to have the preprocessor!
 Would like code to be completely "valid" Verilog.
- Want non-tool users to remain happy.
- Can always edit code without the program.
 Want it trivial to learn basic functions
- Let the user’s pick up new features as they need them.
 Net result: NO disadvantage to using it
- Well adopted, including AMCC, ARM, Agere, Altera, AMD, Analog, Cavium,
Cisco, Cray, Cypress, Freescale, HP, Infineon, Intel, LSI, MIPS, Maxtor, Micron,
NXP, TI, Vitesse, …
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9/25/2009
Idea… Use comments!
wsnyder
The program replaces the text
/*AUTOINST*/ is a
after the comment with the
metacomment.
sensitivity list.
sub s1 (/*AUTOINST*/); sub s1 (/*AUTOINST*/
.i (i),
.o (o));
{edit ports of sub} sub s1 (/*AUTOINST*/
.i (i),
sub s1 (/*AUTOINST*/
.new(new),
.i (i),
.o (o));
.o (o));
If you then edit it, just rerun.
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9/25/2009
Verilog-Mode for Emacs
wsnyder

This expansion is best if in the editor
• You can “see” the expansion and edit as needed

Verilog package for Emacs
• Co-Author Michael McNamara
<[email protected]>
• Auto highlighting of keywords
• Standardized indentation

Reads & expand /*AUTOs*/
• Magic key sequence for inject/expand/deexpand
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9/25/2009
C-c C-z: Inject AUTOs
wsnyder
With this key sequence,
Verilog-Mode adds /*AUTOs*/ to old designs!
always @(en or a) always @(/*AS*/a or ena)
z = a & ena; z = a & ena;
C-c C-z
submod s (.out (out), submod s (.uniq (u),
(or use menu)
.uniq (u), /*AUTOINST*/
.in (in)); // Outputs
.out (out),
// Inputs
.in (in));
GNU Emacs (Verilog-Mode)) GNU Emacs (Verilog-Mode))
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9/25/2009
C-c C-a and C-c C-d
wsnyder
With this key sequence,
Verilog-Mode parses the verilog code, and expands
the text after any /*AUTO*/ comments.
/*AUTOWIRE*/
/*AUTOWIRE*/
wire o;
wire o;
C-c C-a
(or use menu) sub s1 (/*AUTOINST*/
sub s1 (/*AUTOINST*/);
.i (i),
.o (o));
C-c C-d
(or use menu)
GNU Emacs (Verilog-Mode)) GNU Emacs (Verilog-Mode))