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About Verilog
This document provides an overview and outline of a lecture on basic logic design with Verilog. It introduces Verilog as a hardware description language, describes different levels of abstraction in Verilog including gate level and behavioral level modeling. It also outlines topics to be covered such as test benches and provides examples of modeling gates in Verilog.
Detailed Information
| Author: | ['kritti11'] |
|---|---|
| Publication Year: | 2009 |
| Pages: | 46 |
| Language: | English |
| Format: | |
| Price: | FREE |
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