Verification, Abstraction and Reverse Engineering

162 Pages·2017·2.5 MB·English

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Doctoral Dissertations Dissertations and Theses
November 2017
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CUNXI YU
University of Massachusetts Amherst
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FORMAL ANALYSIS OF ARITHMETIC CIRCUITS
USING COMPUTER ALGEBRA
- VERIFICATION, ABSTRACTION AND REVERSE ENGINEERING
A Dissertation Presented
by
CUNXI YU
Submitted to the Graduate School of the
University of Massachusetts Amherst in partial fulfillment
of the requirements for the degree of
DOCTOR OF PHILOSOPHY
September 2017
Electrical and Computer Engineering
(cid:13)c Copyright by Cunxi Yu 2017
All Rights Reserved
FORMAL ANALYSIS OF ARITHMETIC CIRCUITS
USING COMPUTER ALGEBRA
- VERIFICATION, ABSTRACTION AND REVERSE ENGINEERING
A Dissertation Presented
by
CUNXI YU
Approved as to style and content by:
Maciej Ciesielski, Chair
George S. Avrunin, Member
Daniel Holcomb, Member
Sandip Kundu, Member
Christopher V. Hollot, Department Head
Electrical and Computer Engineering
ABSTRACT
FORMAL ANALYSIS OF ARITHMETIC CIRCUITS
USING COMPUTER ALGEBRA
- VERIFICATION, ABSTRACTION AND REVERSE ENGINEERING
SEPTEMBER 2017
CUNXI YU
B.Sc., ZHEJIANG UNIVERSITY CITY COLLEGE
Ph.D., UNIVERSITY OF MASSACHUSETTS AMHERST
Directed by: Professor Maciej Ciesielski
Despite a considerable progress in verification and abstraction of random and
control logic, advances in formal verification of arithmetic designs have been lagging.
This can be attributed mostly to the difficulty in an efficient modeling of arithmetic
circuits and datapaths without resorting to computationally expensive Boolean meth-
ods, suchasBinaryDecisionDiagrams(BDDs)andBooleanSatisfiability(SAT),that
require, bit-blasting, i.e., flattening the design to a bit-level netlist. Approaches that
rely on computer algebra and Satisfiability Modulo Theories (SMT) methods are ei-
thertooabstracttohandlethebit-levelnatureofarithmeticdesignsorrequiresolving
computationally expensive decision or satisfiability problems.
The work proposed in this thesis aims at overcoming the limitations of analyz-
ing arithmetic circuits, specifically at the post-synthesized phase. It addresses the
verification, abstraction and reverse engineering problems of arithmetic circuits at
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an algebraic level, treating an arithmetic circuit and its specification as a properly
constructed algebraic system. The proposed technique solves these problems by func-
tion extraction, i.e., by deriving arithmetic function computed by the circuit from its
low-level circuit implementation using computer algebraic rewriting technique. The
proposed techniques work on large integer arithmetic circuits and finite field arith-
metic circuits, up to 512-bit wide containing millions of logic gates.
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TABLE OF CONTENTS
Page
ABSTRACT.......................................................... iv
LIST OF TABLES .................................................... x
LIST OF FIGURES.................................................. xii
CHAPTER
1. INTRODUCTION ................................................. 1
1.1 Hardware Verification .............................................3
1.2 Verification Techniques ............................................5
1.2.1 Equivalence Checking .......................................5
1.2.2 Model Checking............................................8
1.2.3 Theorem Proving...........................................8
1.2.4 Symbolic Simulation ........................................9
1.2.5 Reverse Engineering .......................................10
1.2.6 Overview of the thesis .....................................12
2. BACKGROUND ................................................. 13
2.1 Canonical Diagrams .............................................13
2.2 SAT and SMT solvers ............................................14
2.3 Structural Minimization ..........................................18
2.4 Computer Algebra Approaches ....................................19
3. FORMAL VERIFICATION OF INTEGER ARITHMETIC
CIRCUITS USING FUNCTION EXTRACTION .............. 25
3.1 Introduction ....................................................25
3.2 Function Extraction .............................................25
3.2.1 Algebraic Model ..........................................26
3.2.2 Outline of the Approach ...................................28
vi
3.2.3 Function extraction vs. Polynomial Division ..................36
3.2.4 Properties of Computed Input Signature .....................39
3.3 Experimental Results ............................................41
3.3.1 Comparison with SAT and SMT ............................41
3.3.1.1 SAT comparison:..................................42
3.3.1.2 SMT experiments .................................44
3.3.2 Limitations and Proposed Solutions..........................45
3.3.2.1 Circuit Boundaries ................................45
3.3.2.2 Output Encoding .................................46
3.3.2.3 Effects of Synthesis on Function Extraction ...........47
3.4 Verification of Datapaths - A Case Study ...........................47
3.4.1 Word-level Verification .....................................50
3.4.2 Bit-level Verification .......................................54
3.4.3 Results ..................................................55
3.5 Conclusions.....................................................56
4. COMPUTER ALGEBRA BASED VERIFICATION WITH
REDUNDANT POLYNOMIALS............................... 59
4.1 Introduction ....................................................59
4.2 Previous Work ..................................................60
4.3 Preliminaries....................................................61
4.3.1 Vanishing Polynomials .....................................63
4.3.2 Don’t-care Polynomials ....................................65
4.4 Sequential Verification ...........................................67
4.4.1 Multiply-Accumulator (MAC) ..............................67
4.4.2 Serial Squarer ............................................69
4.5 Experimental Results ............................................71
4.6 Conclusions.....................................................73
5. ADVANCED ALGEBRAIC REWRITING USING
AND-INV-GRAPH ............................................ 75
5.1 Introduction ....................................................75
5.2 Background.....................................................76
vii
5.2.1 Boolean Network..........................................76
5.2.2 Simplified Polynomial Construction..........................78
5.3 Approach.......................................................79
5.3.1 Outline of the Approach ...................................80
5.3.2 Detecting Redundant Polynomials ...........................82
5.4 Results.........................................................84
5.5 Conclusion .....................................................86
6. ALGEBRAIC SPECTRUM - A NEW CANONICAL
REPRESENTATION OF ARITHMETIC ...................... 87
6.1 Introduction ....................................................87
6.2 Related Work ...................................................89
6.3 Algebraic Spectrum ..............................................93
6.3.1 Uniqueness of Algebraic Spectrum ...........................94
6.3.2 Example - Single Spectrum Function.........................97
6.3.3 Example - Multiple-Spectrum Function.......................99
6.4 Polynomial-Time Spectrum Extraction ............................100
6.5 Results........................................................104
6.6 Conclusion ....................................................106
7. FORMAL ANALYSIS OF FINITE FIELD ARITHMETIC
CIRCUITS ................................................... 107
7.1 Introduction ...................................................107
7.2 Background....................................................109
7.2.1 Galois Field Multiplication ................................109
7.2.2 Irreducible Polynomials ...................................110
7.3 Parallel Extraction in Galois Field ................................112
7.3.1 Computer Algebraic model ................................113
7.3.2 Outline of the Approach ..................................113
7.3.3 Implementation ..........................................117
7.4 Reverse Engineering in Galois Field ...............................120
7.4.1 Output encoding determination ............................121
7.4.2 Input encoding determination..............................122
7.4.3 Extraction of the Irreducible Polynomial ....................124
viii
7.5 Results........................................................127
7.5.1 Parallel Verification of GF(2m) Multipliers...................127
7.5.1.1 Design and Verification cost depend on P(x).........129
7.5.1.2 Runtime vs. Memory of Parallelism.................130
7.5.1.3 Effect of synthesis on verification of GF(2m)
multipliers ...................................131
7.5.2 Reverse Engineering of GF(2m) Multipliers ..................132
7.6 Conclusion ....................................................134
BIBLIOGRAPHY .................................................. 136
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