TLV320ADC3001 Low-Power Stereo ADC With Embedded miniDSP for Wireless Handsets a ...

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TLV320ADC3001
SLAS548D–OCTOBER2008–REVISEDSEPTEMBER2015
TLV320ADC3001 Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
1 Features 1
• StereoAudioADC • 2.24-mm×2.16-mmNanoFree™16-Ball16-YZH
– 92-dBASignal-to-NoiseRatio WaferChipScalePackage(WCSP)
– SupportsADCSampleRatesFrom8kHzto
2 Applications
96kHz
• Instruction-ProgrammableEmbeddedminiDSP • WirelessHandsets
• FlexibleDigitalFilteringWithRAMProgrammable • PortableLow-PowerAudioSystems
Coefficient,Instructions,andBuilt-InStandard • NoiseCancellationSystems
Modes • Front-EndVoiceorAudioProcessorfor Digital
– Low-LatencyIIRFiltersforVoice Audio
– LinearPhaseFIRFiltersforAudio
3 Description
– AdditionalProgrammableIIRFiltersforEQ,
The TLV320ADC3001 device is a low-power, stereo
NoiseCancellation,orReduction
audio analog-to-digital converter (ADC) supporting
– Upto128ProgrammableADCDigital Filter sampling rates from 8 kHz to 96 kHz with an
Coefficients integrated programmable-gain amplifier providing up
• ThreeAudioInputsWithConfigurableAutomatic to 40-dB analog gain or AGC. A programmable
GainControl(AGC) miniDSP is provided for custom audio processing.
Front-end input coarse attenuation of 0 dB, –6 dB, or
– ProgrammableinSingle-EndedorFully
off, is also provided. The inputs are programmable in
DifferentialConfigurations
a combination of single-ended or fully differential
– CanBeDrivenHi-ZforEasyInteroperability configurations. Extensive register-based power
WithOtherAudioICs control is available via I2C, enabling mono or stereo
recording. Low power consumption makes the
• LowPowerConsumptionandExtensiveModular
TLV320ADC3001 ideal for battery-powered portable
PowerControl:
equipment.
– 6-mWMonoRecord8-kHz
– 11-mWStereoRecord,8-kHz DeviceInformation(1)
– 10-mWMonoRecord,48-kHz PARTNUMBER PACKAGE BODYSIZE(NOM)
– 17-mWStereoRecord,48-kHz TLV320ADC3001 DSBGA(16) 2.24mm×2.16mm
• ProgrammableMicrophoneBias (1) For all available packages, see the orderable addendum at
theendofthedatasheet.
• ProgrammablePLLforClockGeneration
• I2CControlBus FunctionalBlockDiagram
• AudioSerialDataBusSupportsI2S,Left/Right-
Processor
Justified, DSP,PCM,andTDMModes
• PowerSupplies:
– Analog:2.6V–3.6V. I2C I2S, LJ, RJ, DSP, TDM
– Digital:Core:1.65V–1.95V,
ADC
I/O:1.1V–3.6V
miniDSP
ADC
TLV320ADC3001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TLV320ADC3001
SLAS548D–OCTOBER2008–REVISEDSEPTEMBER2015 www.ti.com
Table of Contents
1 Features.................................................................. 1 10 DetailedDescription........................................... 13
2 Applications........................................................... 1 10.1 Overview...............................................................13
3 Description............................................................. 1 10.2 FunctionalBlockDiagram.....................................13
4 RevisionHistory..................................................... 2 10.3 FeatureDescription...............................................14
10.4 DeviceFunctionalModes......................................40
5 Description(continued)......................................... 4
10.5 Programming.........................................................40
6 DeviceComparisonTable..................................... 4
10.6 RegisterMaps.......................................................42
7 PinConfigurationandFunctions......................... 5
11 ApplicationandImplementation........................ 74
8 Specifications......................................................... 6
11.1 ApplicationInformation..........................................74
8.1 AbsoluteMaximumRatings......................................6
11.2 TypicalApplication ...............................................74
8.2 ESDRatings..............................................................6
12 PowerSupplyRecommendations..................... 78
8.3 RecommendedOperatingConditions.......................6
13 Layout................................................................... 79
8.4 ThermalInformation..................................................6
13.1 LayoutGuidelines.................................................79
8.5 ElectricalCharacteristics...........................................7
13.2 LayoutExample....................................................79
8.6 DissipationRatings ..................................................8
8.7 I2S/LJF/RJFTiminginMasterMode.........................8 14 DeviceandDocumentationSupport................. 80
8.8 DSPTiminginMasterMode.....................................8 14.1 CommunityResources..........................................80
8.9 I2S/LJF/RJFTiminginSlaveMode...........................9 14.2 Trademarks...........................................................80
8.10 DSPTiminginSlaveMode.....................................9 14.3 ElectrostaticDischargeCaution............................80
8.11 TypicalCharacteristics..........................................12 14.4 Glossary................................................................80
9 ParameterMeasurementInformation................12 15 Mechanical,Packaging,andOrderable
Information........................................................... 80
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionC(April2011)toRevisionD Page
• AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional
Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device
andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1
ChangesfromRevisionB(March2010)toRevisionC Page
• Changedpinoutdiagramtotopview...................................................................................................................................... 5
• Insertedmissingtablereference.......................................................................................................................................... 75
ChangesfromRevisionA(November,2008)toRevisionB Page
• AddedminiDSPtodata-sheettitle.......................................................................................................................................... 1
• AddedminiDSPbullettotheFeatureslist.............................................................................................................................. 1
• AddedasentenceabouttheminiDSPtotheDescriptionsection.......................................................................................... 1
• DeletedYZHandWCSPoptionsfromtheSIMPLIFIEDBLOCKDIAGRAM......................................................................... 4
• AlphabetizedPinFunctionstable........................................................................................................................................... 5
• Changed"complacence"to"compliance"inNote2oftheAbsMaxtable............................................................................. 6
• Changedθ toR ............................................................................................................................................................... 6
JA θJA
• AddedAVDD=3.3VtoElectricalCharacteristicsconditionstatement................................................................................. 7
• Addedinputcommon-modevoltagerowtoElectricalCharacteristicstable.......................................................................... 7
• AddedintegratednoiserowtoElectricalCharacteristics....................................................................................................... 8
• AddedAVDD=3.3VtoElectricalCharacteristicsconditionstatement................................................................................. 8
• AddedmetricdimensionstoNote1oftheDISSIPATIONSRATINGStable......................................................................... 8
• Addedriseandfalltimestothewaveform,Figure1............................................................................................................ 10
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• Addedriseandfalltimestowaveform,Figure2.................................................................................................................. 10
• Addedriseandfalltimestowaveform,Figure3.................................................................................................................. 10
• Changedsignsofnonzeroerrorsin%ERRORcolumn...................................................................................................... 24
ChangesfromOriginal(September2008)toRevisionA Page
• ChangedFigure4-DSPTiminginSlaveMode.AddedtheWCLKtextnote..................................................................... 11
• Removednotefollowingthepage0/register94descriptiontable..................................................................................... 58
• Changedbitvaluesfrom1and2to0and1,respectively................................................................................................... 58
• Listedvalues81through127asreserved........................................................................................................................... 58
• Replacedthelistingofpage-4registers............................................................................................................................... 64
• Addedalistingforpage-5registers...................................................................................................................................... 69
• ChangedFigure44TypicalConnections............................................................................................................................. 74
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5 Description (continued)
The AGC programs to a wide range of attack (7 ms–1.4 s) and decay (50 ms–22.4 s) times. A programmable
noise gate function is included to avoid noise pumping. Low-latency IIR filters optimized for voice and telephony
are available, as well as linear-phase FIR filters optimized for audio. Programmable IIR filters are also available
and may be used for sound equalization, or to remove noise components. The audio serial bus can be
programmed to support I2S, left-justified, right-justified, DSP, PCM, and TDM modes. The audio bus may be
operatedineithermasterorslavemode.
A programmable integrated PLL is included for flexible clock generation and support for all standard audio rates
from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular cases of 12-
MHz,13-MHz, 16-MHz,19.2-MHz,and19.68-MHzsystem clocks.
6 Device Comparison Table
FEATURES TLV320ADC3001 TLV320ADC3101
NumberofADCs 2 2
NumberofInputs/Outputs 3/DigitalI/F 6/DigitalI/F
Resolution(Bits) 24 24
ControlInterface I2C I2C
DigitalAudioInterface LJ,RJ,I2S,DSP,TDM LJ,RJ,I2S,DSP,TDM
DigitalMicrophoneSupport No Yes
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7 Pin Configuration and Functions
YZHPackage
16-PinDSBGA
TopView
A4 B4 C4 D4
A3 B3 C3 D3
A2 B2 C2 D2
A1 B1 C1 D1
PinFunctions
PIN
TYPE DESCRIPTION
NO. NAME
A1 MICBIAS O Microphoneoutputbiasvoltage
A2 RESET I Reset
A3 SCL I/O I2Cserialclock
A4 SDA I/O I2Cserialdatainput/output
B1 IN1R(M) I Analoginput–firstrightsingle-endedordifferentialminusinput
B2 AVDD P Analogvoltagesupply,2.6V–3.6V
B3 DVDD P Digitalcorevoltagesupply,1.65V–1.95V
B4 IOVDD P I/Ovoltagesupply,1.1V–3.6V
C1 IN1L(P) I Analoginput–firstleftsingle-endedordifferentialplusinput
C2 AVSS P Analoggroundsupply,0V
C3 DVSS P Digitalgroundsupply,0V
C4 MCLK I Masterclockinput
D1 IN2L I Analoginput–secondleftsingle-ended
D2 DOUT O Audioserialdatabusdataoutput(output)
D3 WCLK I/O Audioserialdatabuswordclock(input/output)
D4 BCLK I/O Audioserialdatabusbitclock(input/output)
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8 Specifications
8.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
MIN MAX UNIT
AVDDtoAVSS –0.3 3.9 V
IOVDDtoDVSS –0.3 3.9 V
DVDDtoDVSS –0.3 2.5 V
DigitalinputvoltagetoDVSS –0.3 IOVDD+ V
0.3
AnaloginputvoltagetoAVSS –0.3 AVDD+0.3 V
Operatingtemperature –40 85 °C
T Max Junctiontemperature 105 °C
J
Powerdissipation (T Max–T )/θ W
J A JA
T Storagetemperature –65 125 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
8.2 ESD Ratings
VALUE UNIT
Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500
V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±1000 V
C101(2)
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
8.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) Analogsupplyvoltage 2.6 3.3 3.6 V
DVDD(1) Digitalcoresupplyvoltage 1.65 1.8 1.95 V
IOVDD(1) DigitalI/Osupplyvoltage 1.1 1.8 3.6 V
V Analogfull-scale0-dBinputvoltage(AVDD=3.3V) 0.707 Vrms
I
Digitaloutputloadcapacitance 10 pF
T Operatingfree-airtemperature –40 85 °C
A
(1) AnalogvoltagevaluesarewithrespecttoAVSS;digitalvoltagevaluesarewithrespecttoDVSS.
8.4 Thermal Information
TLV320ADC3001
THERMALMETRIC(1) YZH(DSBGA) UNIT
16PINS
R Junction-to-ambientthermalresistance 70.9 °C/W
θJA
R Junction-to-case(top)thermalresistance 0.3 °C/W
θJC(top)
R Junction-to-boardthermalresistance 13.7 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 1.7 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 13.7 °C/W
JB
R Junction-to-case(bottom)thermalresistance — °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report,SPRA953.
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8.5 Electrical Characteristics
At25°C,AVDD=3.3V,IOVDD=1.8V,DVDD=1.8V,f =48-kHz,16-bitaudiodata(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
AUDIOADC
Inputsignallevel(0-dB) Single-endedinput 0.707 Vrms
Inputcommon-modevoltage Single-endedinput 1.35 Vrms
Signal-to-noiseratio, f =48kHz,0-dBPGAgain,IN1inputsselected
S 80 92 dB
A-weighted(1) (2) andAC-shortedtoground
Dynamicrange, f =48kHz,1-kHz–60-dBfull-scaleinput
A-weighted(1) (2) aSppliedatIN1inputs,0-dBPGAgain 92 dB
f =48kHz,1-kHz–2-dBfull-scaleinputapplied –90 –75 dB
S
THD Totalharmonicdistortion atIN1
inputs,0-dBPGAgain 0.003% 0.017%
234Hz,100mV onAVDD,single-endedinput 46
PP
Power-supplyrejectionratio dB
234Hz,100mV onAVDD,differentialinput 68
PP
ADCchannelseparation 1kHz,–2dBIN1LtoIN1R –73 dB
ADCgainerror 1-kHzinput,0-dBPGAgain 0.7 dB
ADCprogrammable-gainamplifier
1-kHzinputtone,R <50Ω 40 dB
maximumgain SOURCE
ADCprogrammable-gainamplifier
0.502 dB
stepsize
IN1inputs,routedtosingleADC
35
Inputmixattenuation=0dB
Inputresistance IN2inputs,inputmixattenuation=0dB 35 kΩ
IN1inputs,inputmixattenuation=–6dB 62.5
IN2inputs,inputmixattenuation=–6dB 62.5
Inputcapacitance 10 pF
Inputlevelcontrolminimum
0 dB
attenuationsetting
Inputlevelcontrolmaximum
6 dB
attenuationsetting
Inputlevelcontrolattenuationstep
6 dB
size
ADCDIGITALDECIMATIONFILTER f =48kHz
S
Filtergainfrom0to0.39f FilterA,AOSR=128or64 ±0.1 dB
S
Filtergainfrom0.55f to64f FilterA,AOSR=128or64 –73 dB
S S
Filtergroupdelay FilterA,AOSR=128or64 17/f s
S
Filtergainfrom0to0.39f FilterB,AOSR=64 ±0.1 dB
S
Filtergainfrom0.60f to32f FilterB,AOSR=64 -46 dB
S S
Filtergroupdelay FilterB,AOSR=64 11/f s
S
Filtergainfrom0to0.39f FilterC,AOSR=32 ±0.033 dB
S
Filtergainfrom0.28f to16f FilterC,AOSR=32 -60 dB
S S
Filtergroupdelay FilterC,AOSR=32 11/f s
S
MICROPHONEBIAS
2
2.25 2.5 2.75
Biasvoltage Programmablesettings,load=750Ω V
AVDD
–0.2
Currentsourcing 2.5Vsetting 4 mA
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlowpassfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelowpassfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
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Electrical Characteristics (continued)
At25°C,AVDD=3.3V,IOVDD=1.8V,DVDD=1.8V,f =48-kHz,16-bitaudiodata(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
BW=20Hzto20kHz,A-weighted,1-µF µVr
Integratednoise 3.3
capacitorbetweenMICBIASandAGND ms
DIGITALI/O
0.3×
V Inputlowlevel I =5μA –0.3 V
IL IL IOVDD
V Inputhighlevel(3) I =5μA 0.7× V
IH IH IOVDD
0.1×
V Outputlowlevel I =2TTLloads V
OL IH IOVDD
0.8×
V Outputhighlevel I =2TTLloads V
OH OH IOVDD
SUPPLYCURRENT f =48kHz,AVDD=3.3V,DVDD=IOVDD=1.8V
S
AVDD 2
Monorecord PLLandAGCoff mA
DVDD 1.9
AVDD 4
Stereorecord PLLandAGCoff mA
DVDD 2.1
AVDD Additionalpowerconsumedwhen 1.1
PLL mA
DVDD PLLispowered 0.8
AVDD Allsupplyvoltagesapplied,allblocks 0.04
Powerdown μA
DVDD programmedinlowestpowerstate 0.7
(3) WhenIOVDD<1.6V,minimumV is1.1V.
IH
8.6 Dissipation Ratings(1)
T =25°C T =75°C T =85°C
PACKAGETYPE A DERATINGFACTOR A A
POWERRATING POWERRATING POWERRATING
DSBGA 1052.6mW 13.1mW/°C 394.7mW 263.2mW
(1) Thisdatawastakenusing2oz.(0.071-mmthick)traceandcopperpadthatissoldereddirectlytoaJEDECstandard4-layer3-in.×3-
in.(7.62-cm×7.62-cm)PCB.
8.7 I2S/LJF/RJF Timing in Master Mode
Specifiedat25°C,DVDD=1.8V.Alltimingspecificationsaremeasuredatcharacterization.SeeFigure1fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 20 15 ns
d
t (DO-WS) BCLK/WCLKtoDOUTdelaytime 25 20 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 20 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
8.8 DSP Timing in Master Mode
Specifiedat25°C,DVDD=1.8V.Alltimingspecificationsaremeasuredatcharacterization.SeeFigure2fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 25 15 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 25 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
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8.9 I2S/LJF/RJF Timing in Slave Mode
Specifiedat25°C,DVDD=1.8V.Alltimingspecificationsaremeasuredatcharacterization.SeeFigure3fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKsetuptime 10 6 ns
s
t (WS) BCLK/WCLKholdtime 10 6 ns
h
BCLK/WCLKtoDOUTdelaytime(for
t (DO-WS) 30 30 ns
d LJFModeonly)
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 16 8 ns
r
t Falltime 16 8 ns
f
8.10 DSP Timing in Slave Mode
Specifiedat25°C,DVDD=1.8V.Alltimingspecificationsaremeasuredatcharacterization.SeeFigure4fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKsetuptime 10 8 ns
s
t (WS) BCLK/WCLKholdtime 10 8 ns
h
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 15 8 ns
r
t Falltime 15 8 ns
f
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WCLK
t(WS)
d
t t
r f
BCLK
t(DO-WS) t(DO-BCLK)
d d
DOUT
Figure1. I2S/LJF/RJFTiminginMasterMode
WCLK
t(WS) t(WS)
d d
t t
f r
BCLK
t(DO-BCLK)
d
DOUT
Figure2. DSPTiminginMaster Mode
WCLK
t (WS)
S
t (WS)
h
t (BCLK)
H
t t
r f
BCLK
t (BCLK) t (DO-WS)
L d
t (DO-BCLK)
d
DOUT
Figure3. I2S/LJF/RJFTiminginSlaveMode
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