Testing Static Random Access Memories: Defects, Fault Models and Test Patterns

231 Pages·2004·6.267 MB·English

by  Said Hamdioui (auth.)

TESTING STATIC RANDOM ACCESS MEMORIES
FRONTIERS IN ELECTRONIC TESTING
Consulting Editor
Vishwani D. Agrawal
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TESTING STATIC RANDOM ACCESS
MEMORIES
DEFECTS, FAULT MODELS AND TEST PATTERNS
by
SAID HAMDIOUI
Delft University ofT echnology, The Netherlands
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5430-5 ISBN 978-1-4757-6706-3 (eBook)
DOI 10.1007/978-1-4757-6706-3
Printed on acid-free paper
All Rights Reserved
© 2004 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, Boston in 2004
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception
of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
To my parents
Contents
Preface xi
xv
Acknowledgements
xvii
Symbols and notations
I Introductory 1
1 Introduction 3
1.1 Test philosophy ....... . 4
1.2 Memory technology. . . . . . 6
1.2.1 Memory classification 6
1.2.2 Semiconductor memories 8
1.3 Modeling and testing faults in SRAMs 11
1.3.1 Single-port SRAM testing 11
1.3.2 Multi-port SRAM testing .. 12
2 Semiconductor memory architecture 17
2.1 Memory models ....... . 18
2.2 External memory behavior. . . . . . 19
2.3 Functional memory behavior .... 21
2.3.1 Functional SP SRAM model 21
2.3.2 Functional MP SRAM model 22
2.4 Electrical memory behavior ..... 23
2.4.1 Electrical structure for SP SRAMs 23
2.4.2 Electrical structure for MP SRAMs 29
2.5 Memory process technology 34
3 Space of memory faults 37
3.1 Concept of fault primitive . . . . . . 38
3.2 Classification of fault primitives . . . 39
3.2.1 Static versus dynamic faults. 40
3.2.2 Simple versus linked faults .. 40
Vll
viii CONTENTS
3.2.3 Single-port versus multi-port faults. 41
3.2.4 Single-cell versus multi-cell faults . 41
3.3 Single-port faults . . . . . . . . . . .... 42
3.3.1 Single-cell fault primitives . . . .. 43
3.3.2 Single-cell functional fault models 44
3.3.3 Two-cell fault primitives . . . . . 47
3.3.4 Two-cell functional fault models 49
3.4 Two-port fault primitives .... . .. . 52
3.4.1 Single-cell fault primitives ... . 53
3.4.2 Single-cell functional fault models 55
3.4.3 Two-cell fault primitives . . . . . 57
3.4.4 Two-cell functional fault models 60
3.4.5 Three-cell fault primitives . . . . . 63
3.4.6 Three-cell functional fault models . 64
4 Preparation for circuit simulation 65
4.1 Selected multi-port SRAM cell 66
4.2 Modeling of spot defects . . . . . 66
4.3 Definition and location of opens . 68
4.3.1 Opens within a cell .... 68
4.3.2 Opens at bit lines and word lines 70
4.4 Definition and location of shorts ... . 71
4.4.1 Shorts within a cell ....... . 71
4.4.2 Shorts at bit lines and at word lines 71
4.5 Definition and location of bridges . 72
4.5.1 Bridges within a cell . 73
4.5.2 Bridges between cells. 73
4.6 Simulation model . . . . . 75
4.7 Simulation methodology . 77
4.7.1 Single-cell defects. 78
4.7.2 Multi-cell defects . 80
4.8 Simulation results for the fault free case 81
II Testing single-port and two-port SRAMs 85
5 Experimental analysis of two-port SRAMs 87
5.1 The to-be simulated spot defects 88
5.2 Simulation results ........ . 90
5.3 Realistic fault models ...... . 93
5.3.1 Realistic single-port faults. 93
5.3.2 Realistic two-port faults . . 97
5.4 Fault probability analysis . . . . . 99
5.4.1 SDs equally likely to occur 99
5.4.2 Extraction of SDs by IFA 101
CONTENTS ix
6 Tests for single-port and two-port SRAMs 105
6.1 Notation for march tests ........ . 106
6.2 Tests for single-port faults ....... . 108
6.2.1 Effectiveness of traditional tests. 108
6.2.2 March SR+ and March SRD+ . 110
6.2.3 March SS . . . . . . . . . . . . . 113
6.3 Conditions for detecting two-port faults 115
6.3.1 Conditions for detecting 2PF1s 115
6.3.2 Conditions for detecting 2PF2s 118
6.4 Tests for two-port faults .. 122
6.4.1 Tests for the 2PF1s ... . 122
6.4.2 Tests for the 2PF2s ... . 123
6.4.3 Classification of 2PF tests . 128
6.4.4 Summary of 2P tests . 130
6.5 Comparison with other tests. . . . 130
6.6 Test strategy . . . . . . . . . . . . 132
6.7 Test results versus fault probabilities 132
7 Testing restricted two-port SRAMs 135
7.1 Classification of two-port memories ....... . 136
7.2 Realistic faults for restricted 2P memories ... . 136
7.2.1 Realistic 2PFs for two-read 2P memories 137
7.2.2 Realistic 2PFs for single-read 2P memories 138
7.3 Tests for restricted two-port memories ..... 138
7.3.1 Tests for two-read two-port memories . 139
7.3.2 Tests for single-read two-port memories 139
7.4 Test strategy for restricted two-port memories. 141
7.4.1 Test strategy for two-read 2P memories 141
7.4.2 Test strategy for single-read 2P memories 142
III Testing p-port SRAMs 147
8 Experimental analysis of p-port SRAMs 149
8.1 The to-be simulated spot defects .... . 150
8.2 Simulation results ............ . 151
8.3 Realistic fault models for three-port memories. 153
8.3.1 Realistic three-port faults .... . 154
8.4 Fault probabilities analysis ....... . 156
8.5 Realistic fault models for p-port memories 159
9 Tests for p-port SRAMs 161
9.1 Condition for detecting p-port faults 162
9.1.1 Condition for detecting pPF1s 163
9.1.2 Condition for detecting pPF2s 163
9.2 Tests for p-port faults . 165
9.2.1 Tests for pPF1s . 165
9.2.2 Tests for pPF2s . 166
9.2.3 Test for all pPFs 170
x CONTENTS
9.2.4 Summary of pP tests. 171
9.3 Test strategy . . . . . . . . . 171
10 Testing restricted p-port SRAMs 175
10.1 Classification of p-port memories ...... . 176
10.2 Realistic faults for restricted p-port memories 177
10.2.1 The pPFs for p-read pP memories .. 177
10.2.2 The pPFs for (p - I)-read pP memories 178
10.2.3 The pPFs for other pP memories classes 179
10.3 Tests for restricted p-port memories .. . 179
10.3.1 Tests for p-read pP memories ... . 179
10.3.2 Tests for (p - I)-read pP memories. 179
10.4 Test strategy for restricted p-port memories 180
10.4.1 Test strategy for p-read pP memories. 180
10.4.2 Test strategy for (p - I)-read pP memories 181
10.4.3 Test strategy for other pP memories 183
11 Trends in embedded memory testing 185
11.1 Introduction ......... . 186
11.2 Fault modeling ........... . 187
11.2.1 Dynamic fault models ... . 189
11.2.2 Other fault modeling aspects 189
11.3 Test algorithm design .. 191
11.4 Built-in-self test (BIST) . 192
11.5 Built-in-self-repair (BISR) 193
11.6 Putting all together 196
Bibliography 197
A Simulation results for two-port SRAMs 205
A.1 Simulation results for opens . 206
A.2 Simulation results for shorts . 208
A.3 Simulation results for bridges 209
B Simulation results for three-port SRAMs 213
B.1 Simulation results for opens and shorts. 214
B.2 Simulation results for bridges . . . . . . . 214
Index 219