synthesis and place and route optimization techniques for arithmetic based operators

120 Pages·2005·3.97 MB·English

SYNTHESIS AND PLACE AND ROUTE
OPTIMIZATION TECHNIQUES FOR
ARITHMETIC BASED OPERATORS
Student: Alberto Bonanno
Project supervisor: Alain Vachoux
Contents
1 Introduction 1
2 Filter FIR (Finite Impulse Response) 3
2.1 Analog vs Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Mathematical approach . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 FIR vs IIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 FIR Transposed Form . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 VLSI design (cid:29)ow 10
3.1 Introduction on Bottom-up and Top-down design (cid:29)ow . . . . . . . . . 10
3.2 Overview on the design (cid:29)ow discussed in this diploma work . . . . . . 14
4 Timing Optimization at synthesis level 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Design (cid:29)ow for timing optimization . . . . . . . . . . . . . . . . . . . 18
5 Place and Route. Timing Optimization Techniques 31
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Placement and routing without optimization. The basic (cid:29)ow. The
analysis of the complete design. . . . . . . . . . . . . . . . . . . . . . 33
5.3 The e(cid:27)ect of CTGEN introduction . . . . . . . . . . . . . . . . . . . 43
5.4 The timing optimization techniques during placement and routing . . 50
6 Power consumption 54
6.1 Introduction. Power consumption in VLSI design. . . . . . . . . . . . 54
6.2 Power Optimization using RTL-backward SAIF . . . . . . . . . . . . 57
6.3 Power Optimization using gatelevel-backward SAIF . . . . . . . . . . 64
I
7 Future work 67
8 Script for Synopsys and Cadence 68
8.1 BASIC SCRIPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2 DESIGN FLOW WITH CLOCK TREE . . . . . . . . . . . . . . . . 76
8.3 FLOWCOMPLETEWITHTIMINGOPT.ANDTIMING-DRIVEN
PLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.4 SCRIPT FOR PLACE AND ROUTE EXTREME . . . . . . . . . . . 95
8.5 POWER ESTIMATION AND OPTIMIZATION . . . . . . . . . . . . 108
8.6 TO CAPTURE SWITCHING ACTIVITY . . . . . . . . . . . . . . . 111
8.7 SCRIPT FOR SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . 112
Bibliography 117
II
Chapter 1
Introduction
Timing, energy consumption, and area are the main parameters of interest for any
digital circuit designer. Circuit timing is usually considered the most important;
most often, the timing requirement is stated as a maximum cycle time or minimum
operating frequency. However, at the placement stage of the design process, people
commonly tries to achieve the best possible timing performance regardless of the
constraint and it is important to be able to guarantee that the timing speci(cid:28)cation
is met. Usually, energy optimization is then performed secondarily.
By contrast, sometimes it can be desirable to minimize energy model consump-
tion and don’t give great importance to satisfy the timing constraint. For example,
a designer of a wireless cryptographic card may care most about energy per en-
cryption. Therefore the importance of timing or power optimization depends on
the (cid:28)nal application of the design and the knowledge of di(cid:27)erent techniques became
fundamental for strict constrained design.
The demand for timing-constrained energy optimization is not of recent origin;
however, asCMOStechnologyimproves, thenatureofenergyconsumptionindigital
ICs changes. Since traditional CMOS interconnect performance does not scale as
well as device performance, new technologies and computer-aided design solutions
must focus on interconnect. Speci(cid:28)cally, as new interconnect technologies appear,
design tools must be able to exploit them for optimal performance.
The goal of this work is to investigate the capabilities provided by commercial
synthesis (Synopsys Design Compiler) and place and route (Cadence Silicon Ensem-
ble) tools to optimize the design of a FIR (cid:28)lter described as a VHDL RTL model. A
1
1 (cid:21) Introduction
description of di(cid:27)erent optimal design (cid:29)ows is reported in this paper to give designer
the possibility of choosing the best solution considering his design constraints. The
starting point is an existing synthesizable VHDL RTL model that implements a 8-
tap Finite Impulse Response (cid:28)lter based on 16-bit input samples and 14-bit signed
coe(cid:30)cients. The (cid:28)lter architecture implements a transposed form using pipelined
cascaded adders. Multiplications are implemented as constant coe(cid:30)cients multipli-
ers using pre-computed partial products of the (cid:28)xed coe(cid:30)cients stored in ROM.
Timing-driven and power-driven synthesis and place and route techniques will be
used to achieve the best possible layout achieving speed and/or power consumption
trade-o(cid:27)s. The design kit will be UMC logic 0.18µ CMOS.
At (cid:28)rst, an analysis of the VHDL code will be performed to explain the structure
of the (cid:28)lter FIR realized. This structure has been suggested by a Xilinx study
about an high-speed, full-precision, Transposed Form FIR (cid:28)lter design implemented
in FPGA. Afterwards, a description of the simplest design (cid:29)ow of a VLSI circuit
will be made and a general view on the principal problem of the VLSI design will
be given. Then optimization techniques at the synthesis level will be performed to
achieve the maximum frequency that is possible considering is only the (cid:28)rst step
to design a chip physically. The value of the slack calculated with "Prime-Time"
assumes an importance not only in the Synthesis step to create a good netlist, but
also in the Place&Route step to preserve the functionality of the circuit. In the
chapter that treats placing and routing technique, the clock-tree generation is also
showed because it’s a necessary step to reduce clock-skew e(cid:27)ect. Three di(cid:27)erent
script for Cadence Silicon Ensemble have been realized and the di(cid:27)erent layout
results are described in the chapter number 5. At the end of the (cid:29)ow, the possibility
of creating a custom wire load model, based on the realized circuit, is considered and
the results at synthesis level are described. This new model, created using the layout
dataonwirecapacitanceandthelastverilognetlist,isatablebasedonanestimation
of the fanout in the design in relation with wire length,wire capacitance and wire
resistance. However, because of the great trade of portable application, the design
constraints can also require to minimize the power consumption after or instead
timing optimization. Consequently, an entire chapter is consecrated to describe the
modi(cid:28)cations in the Synopsys design (cid:29)ow to achieve the required speci(cid:28)cations in
power terms.
2
Chapter 2
Filter FIR (Finite Impulse Response)
2.1 Analog vs Digital Filter
Insignalprocessing, thefunctionofa(cid:28)lteristoremoveunwantedpartsofthesignal,
such as random noise, or to extract useful part of the signal, such as the components
lying within a certain frequency range. There are two main kinds of (cid:28)lter, analog
and digital. They are quite di(cid:27)erent in their physical makeup and in how they work.
An analog (cid:28)lter uses analog electronic circuits made up from components such
as resistors, capacitors and op amps to produce the required (cid:28)ltering e(cid:27)ect. Such
(cid:28)lter circuits are widely used in such applications as noise reduction, video signal
enhancement, graphic equalizers in hi-(cid:28) systems, and many other areas. There are
well-established standard techniques for designing an analog (cid:28)lter circuit for a given
requirement. At all stages, the signal being (cid:28)ltered is an electrical voltage or current
which is the direct analogue of the physical quantity involved.
A digital (cid:28)lter uses a digital processor to perform numerical calculations on
sampled values of the signal. The processor may be a general-purpose computer
such as a PC, or a specialized DSP (Digital Signal Processor) chip. The analog in-
put signal must (cid:28)rst be sampled and digitized using an ADC. The resulting binary
numbers, representing successive sampled values of the input signal, are transferred
to the processor, which carries out numerical calculations on them. These calcu-
lations typically involve multiplying the input values by constants and adding the
products together. If necessary, the results of these calculations, which now repre-
sent sampled values of the (cid:28)ltered signal, are output through a DAC to convert the
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2 (cid:21) Filter FIR (Finite Impulse Response)
signal back to analog form.
The digital (cid:28)lters present some advantages that make preferable their use over
the analog technology and con(cid:28)ne analog (cid:28)lters to high frequency applications. The
main advantage can be summarized in the follow list.
• A digital (cid:28)lter can be programmable and this means it can easily be changed
without a(cid:27)ecting the circuitry (hardware).
• Digital(cid:28)ltersareeasilydesigned, testedandimplementedonageneral-purpose
computer or workstation.
• Thecharacteristicsofanalog(cid:28)ltercircuits(particularlythosecontainingactive
components) are subject to drift and are dependent on temperature. Digital
(cid:28)ltersdonotsu(cid:27)erfromthisproblemsandsoareextremelystablewithrespect
both to time and temperature.
• Fast DSP processors can handle complex combinations of (cid:28)lters in parallel or
cascade, making the hardware requirements relatively simple and compact in
comparison with the equivalent analog circuitry.
In this diploma project, the e(cid:27)ort is focalized on the design of a digital (cid:28)lter FIR
and so only a digital approach on the waste domain of (cid:28)lters will be made.
4
2 (cid:21) Filter FIR (Finite Impulse Response)
2.2 Mathematical approach
A digital (cid:28)lter is just a (cid:28)lter that operates on digital signals. It is a computation
whichtakesonesequenceofnumbers(theinputsignal)andproducesanewsequence
of numbers (the (cid:28)ltered output signal). It can be represented by the generic discrete
time equation
J K
X X
y[n] = α x[n−j]+ β y[n−k] (2.1)
j k
j=0 k=1
or its impulse response
J K
X X
h[n] = α δ[n−j]+ β h[n−k] (2.2)
j k
j=0 k=1
Depends on the value of the coe(cid:30)cients α and β , the Digital Filter assumes
j k
di(cid:27)erent characteristics. If the current output (y ) is calculated from the current
n
and previous input values (x , x , x , ...), the type of (cid:28)lter is said to be non-
n n−1 n−2
recursive(FIR). Whereas, if the (cid:28)lter uses previous output values in addition to
input values, it is a recursive (cid:28)lter(IIR). The biggest parameter between J and
K represents the order of the (cid:28)lter that can be de(cid:28)ned as the largest number of
previous input or output values required to compute the current output.
Usually, the Z-Transform is used to represent the digital (cid:28)lter in the frequency
domain and so the equations 2.1 assumes the following form
J K
Y(z) = Xα z−jX(z)+ Xβ z−kY(z) (2.3)
j k
j=0 k=1
and the system transfer function becomes now
Y(z) PJ α z−j
H(z) = = j=0 j (2.4)
X(z) 1−PK β z−k
k=1 k
In the Z-Domain, the operator z−1 holds fundamental importance because it
represents an unit delay in the Discrete Time Domain. It is preferable the represen-
tation in the Z-Domain because it makes possible a simple analysis of the stability
of (cid:28)lters.
5
2 (cid:21) Filter FIR (Finite Impulse Response)
2.3 FIR vs IIR
Some people prefer an alternative terminology in which a non-recursive (cid:28)lter is
known as a FIR ( Finite Impulse Response ) (cid:28)lter, and a recursive (cid:28)lter as an IIR
( In(cid:28)nite Impulse Response ) (cid:28)lter. These terms refer to the di(cid:27)ering "impulse
responses" of the two types of (cid:28)lter. The impulse response of a digital (cid:28)lter is
the output sequence from the (cid:28)lter when a unit impulse is applied at its input.
A FIR (cid:28)lter is one whose impulse response is of (cid:28)nite duration. An IIR (cid:28)lter is
one whose impulse response theoretically continues forever because the recursive
(previous output) terms feed back the value into the (cid:28)lter input and keep it going.
The term IIR is not very accurate because the actual impulse responses of nearly
all IIR (cid:28)lters reduce virtually to zero in a (cid:28)nite time. Nevertheless, these two terms
are widely used.
From this explanation, it might seem as recursive (cid:28)lters are more complicated
and require more calculations to be performed, since there are previous output
terms in the (cid:28)lter expression as well as input terms. In reality, to achieve a desired
characteristic response using a recursive (cid:28)lter generally requires a much lower order
(cid:28)lter(andthereforefewertermstobeevaluatedbytheprocessor)thantheequivalent
non-recursive (cid:28)lter.
A simple example of a recursive digital (cid:28)lter is given by
y = x +y (2.5)
n n n−1
This example demonstrates an important and useful feature of recursive (cid:28)lters:
the economy with which the output values are calculated, as compared with the
equivalent non-recursive (cid:28)lter. In this example, each output is determined simply
by adding two numbers together. For instance, to calculate the output at time
t=10h, the recursive (cid:28)lter uses the expression
y = x +y (2.6)
10 10 9
6
2 (cid:21) Filter FIR (Finite Impulse Response)
To achieve the same e(cid:27)ect with a non-recursive (cid:28)lter would be necessary using
the expression
y = x +x +x +x +x +x +x +x +x +x +x (2.7)
10 10 9 8 7 6 5 4 3 2 1 0
and so many more addition operations as well as the storage of many more values
in memory have to be performed. The most important advantage of FIR (cid:28)lters is
their guaranteed stability.
7