Table Of ContentLuca Gaetano Amaru
New Data
Structures and
Algorithms for
Logic Synthesis
and Verification
New Data Structures and Algorithms for Logic
fi
Synthesis and Veri cation
Luca Gaetano Amaru
New Data Structures
and Algorithms for Logic
fi
Synthesis and Veri cation
123
Luca Gaetano Amaru
SynopsysInc.
SantaClara, CA
USA
ISBN978-3-319-43173-4 ISBN978-3-319-43174-1 (eBook)
DOI 10.1007/978-3-319-43174-1
LibraryofCongressControlNumber:2016946018
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Success is not final, failure is not fatal:
It is the courage to continue that counts.
—Winston Churchill
To my parents
Preface
The strong interaction between Electronic Design Automation (EDA) tools and
Complementary Metal-Oxide Semiconductor (CMOS) technology contributed
substantially to the advancement of modern digital electronics. The continuous
downscaling of CMOS Field Effect Transistor (FET) dimensions enabled the
semiconductor industry to fabricate digital systems with higher circuit density at
reduced costs. To keep pace with technology, EDA tools are challenged to handle
both digital designs with growing functionality and device models of increasing
complexity. Nevertheless, while the downscaling of CMOS technology requires
more complex physical design models, the logic abstraction of a transistor as a
switchhasnotchangedevenwiththeintroductionof3DFinFETtechnology.Asa
consequence, modern EDA tools are fine-tuned for CMOS technology and the
underlying design methodologies are based on CMOS logic primitives, i.e., neg-
ativeunatelogicfunctions.WhileitisclearthatCMOSlogicprimitiveswillbethe
ultimate building blocks for digital systems in the next 10 years, no evidence is
providedthat CMOSlogic primitives arealso theoptimal basis for EDA software.
In EDA, the efficiency of methods and tools is measured by different metrics such
as (i) the result quality, for example the performance of an automatically synthe-
sized digital circuit, (ii) the runtime, and (iii) the memory footprint on the host
computer.Withtheaimtooptimizethesemetrics,theaccordancetoaspecificlogic
modelisnolongerimportant.Indeed,thekeytothesuccessofanEDAtechniqueis
the expressive power of the logic primitives’ handling and solving the problem,
which determines the capability to reach better metrics.
In this book, we investigate new logic primitives for electronic design
automation tools.
We improve the efficiency of logic representation, manipulation, and opti-
mization tasks by taking advantage of majority and biconditional logic primitives.
We develop synthesis tools exploiting the majority and biconditional logic
expressiveness. Our tools show strong results as compared to state-of-the-art aca-
demicandcommercialsynthesistools.Indeed,weproducethebest(public)results
for many circuits in combinational benchmark suites. On top of the enhanced
ix
x Preface
synthesis power, our methods are also the natural and native logic abstraction for
circuit design in emerging nanotechnologies, where majority and biconditional
logic are the primitive gates for physical implementation.
We accelerate formal methods by (i) studying core properties of logic circuits
and (ii) developing new frameworks for logic reasoning engines. Thanks to the
majority logic representation theory, we prove nontrivial dualities for the property
checking problem of logic circuits. Our findings enable sensible speedups in
solvingcircuitsatisfiability.Withtheaimofexploitingfurthertheexpressivepower
ofmajoritylogic,wedevelopanalternativeBooleansatisfiabilityframeworkbased
onmajorityfunctions.Weprovethatthegeneralproblemisstillintractable,butwe
show practical restrictions that instead can be solved efficiently. Finally, we focus
ontheimportantfieldofreversiblelogicwhereweproposeanewapproachtosolve
the equivalence checking problem. We define a new type of reversible miter over
which the equivalence test is performed. Also, we represent the core checking
problem in terms of biconditional logic. This enables a much more compact for-
mulationoftheproblemascomparedtothestateoftheart.Indeed,ittranslatesinto
more than one order of magnitude speedup for the equivalence checking task, as
compared to the state-of-the-art solution.
WearguethatnewapproachestosolvecoreEDAproblemsarenecessary,aswe
havereachedapointintechnologywherekeepingpacewithdesigngoalsistougher
than ever.
Santa Clara, USA Luca Gaetano Amaru
Acknowledgments
I would like to express my sincere gratitude to my advisor Prof. Giovanni De
Micheli for giving me the opportunity to pursue doctoral studies within the
Integrated Systems Laboratory (LSI) at EPFL. His guidance, motivation, and
immense knowledge helped me in all time of research. I could not have imagined
having a better advisor and mentor for my Ph.D. studies. I am thankful to my
co-advisor, Prof. Andreas Burg, for his valuable advice and encouragement.
Besides my advisors, I would like to thank Dr. Pierre-Emmanuel Gaillardon,
who provided me tremendous support and guidance through my doctoral studies.
Without his precious help this book would not have been possible.
Furthermore, I am very grateful to Prof. Subhasish Mitra for the inspiring dis-
cussions on the interaction between EDA and nanotechnologies and for giving me
the opportunity to be a visiting student at Stanford University.
I would like to express my deepest appreciation to Prof. Maciej Ciesielski, Dr.
Alan Mishchenko, Prof. Anupam Chattopadhyay, Dr. Robert Wille, and Dr.
MathiasSoekenforthegreatresearchcollaborationswehad,whicharealsopartof
this book.
My sincere thanks also go to Profs. Paolo Ienne, Joseph Sifakis, Subhasish
Mitra, and Enrico Macii for their insightful comments on this work.
Last but not least, I would like to thank my parents for their unconditional love
and continuous support.
xi
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Electronic Design Automation. . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Modern EDA Tools and Their Logic Primitives . . . . . . . . . . . . . 3
1.2.1 Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Formal Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Impact on Modern CMOS Technology . . . . . . . . . . . . . . 5
1.3.2 Impact on Beyond CMOS Technologies . . . . . . . . . . . . . 5
1.4 Contributions and Position with Respect to Previous Work. . . . . . 7
1.4.1 Logic Representation, Manipulation and Optimization . . . . 7
1.4.2 Boolean Satisfiability and Equivalence Checking. . . . . . . . 8
1.5 Book Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Part I Logic Representation, Manipulation and Optimization
2 Biconditional Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1 Binary Decision Diagrams . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.2 Emerging Technologies . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Biconditional Binary Decision Diagrams . . . . . . . . . . . . . . . . . . 21
2.3.1 Biconditional Expansion . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 BBDD Structure and Ordering . . . . . . . . . . . . . . . . . . . . 22
2.3.3 BBDD Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.4 BBDD Complemented Edges . . . . . . . . . . . . . . . . . . . . . 27
2.3.5 BBDD Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 BBDD Representation: Theoretical and Experimental Results . . . . 33
2.4.1 Theoretical Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.4.2 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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