Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects

171 Pages·2004·5.22 MB·English

Multi-Gbit/s CMOS Transimpedance Amplifier
with Integrated Photodetector for Optical Interconnects

A Ph. D. Thesis Presented to The Academic Faculty
by
Indal Song

In Partial Fulfillment of the Requirement for the Degree of
Doctor of Philosophy in Electrical and Computer Engineering

Georgia Institute of Technology
November, 2004
Multi-Gbit/s CMOS Transimpedance Amplifier
with Integrated Photodetector for Optical Interconnects

Approved by:

Dr. Martin A. Brooke School of Electrical and Computer Engineering
Dr. Stephen P. DeWeerth School of Electrical and Computer Engineering
Dr. David E. Schimmel School of Electrical and Computer Engineering
Dr. David S. Citrin School of Electrical and Computer Engineering
Dr. Paul A. Kohl School of Chemical and Biomolecular Engineering

Novermber 19, 2004
ACKNOWLEDGEMENTS
This dissertation could not have been written without Dr. Martin A. Brooke who
not only served as my research advisor but also encouraged and challenged me
throughout my graduate program.
During the course of my stay at Georgia Institute of Technology, he and the other
distinguished faculty members, Dr. Nan M. Jokerst, Dr. Stephen P. DeWeerth, Dr. David
E. Schimmel, Dr. David Citrin, and Dr. Paul A. Kohl patiently guided me through the
dissertation process, never accepting less than my best efforts. I would like to express my
appreciation to them.
I’m also grateful that I had opportunities to work with my colleagues/friends,
Seokhun Hyun, Daeik Kim, Ananthasayanam Chellappa, Jaemin Shin, Jaehong Kim,
Cheolung Cha, and Sungyong Jung for their help and valuable inputs towards this work. I
thank them all.
Finally, I would like to take this opportunity to thank my wife, Sunwook, and my
daughter, Irene, for their continuous support and all the joy that they bring into my life.

November 19, 2004

iii
TABLE OF CONTENTS
ACKNOWLEDGEMENTS...............................................................................................iii
LIST OF TABLES.............................................................................................................vi
LIST OF FIGURES..........................................................................................................vii
SUMMARY.......................................................................................................................ix
CHAPTER I INTRODUCTION.................................................................................1
1.1 Generic Fiber Optic Communication System..............................................3
1.2 Objectives....................................................................................................5
CHAPTER II BACKGROUND AND DESIGN CONSIDERATION........................7
2.1 Background..................................................................................................7
2.1.1 Photodetectors..................................................................................8
2.1.2 Characteristics of Preamplifier......................................................10
2.1.3 Sensitivity and Bit-error-rate.........................................................11
2.1.4 Eye Diagram..................................................................................15
2.2 Noise Consideration...................................................................................19
2.2.1 Device Intrinsic Noise....................................................................20
2.2.2 Noise Requirements.......................................................................21
2.2.3 Noise and Bandwidth Trade-off.....................................................25
CHAPTER III DESIGN OF OPTICAL PREAMPLIFIER CIRCUIT........................28
3.1 Introduction................................................................................................28
3.2 Transimpedance Stage...............................................................................30
3.2.1 Principal Preamplifier Topologies.................................................30
3.2.1.1 High Impedance Open-loop Amplifier..............................31
3.2.1.2 Low Impedance Open-loop Amplifier...............................33
3.2.1.3 Transimpedance Feedback Amplifier................................35
3.2.2 Differential Topology....................................................................39
3.2.3 Co-Design of Frontend..................................................................42
3.2.3.1 Quantum Efficiency and Bandwidth..................................43
iv
3.2.3.2 Optimized Sensitivity.........................................................45
3.2.4 Transimpedance Amplifier Design................................................49
3.3 Post-amplifier and Output Buffer..............................................................52
3.3.1 Cascaded Amplifier.......................................................................53
3.3.2 Bandwidth Enhancement...............................................................55
3.3.2.1 Cherry-Hooper Amplifier..................................................56
3.3.2.2 Capacitive Peaking.............................................................58
3.3.2.3 Source Degeneration..........................................................60
3.3.2.4 Inductive Peaking...............................................................62
3.3.3 Post-amplifier Design....................................................................65
3.3.4 Output Buffer Design.....................................................................68
CHAPTER IV SIMULATIONS, LAYOUT, AND MEASUREMENTS....................70
4.1 Simulations......................................................................................................70
4.1.1 HPADS Simulation........................................................................70
4.1.2 HSPICE Transient Simulation.......................................................73
4.1.3 AC and Noise Simulation..............................................................80
4.1.4 Packaging Effect Simulation..........................................................85
4.2 Layout 88
4.3 Measurements..................................................................................................91
4.3.1 Measurement Setup........................................................................91
4.3.2 Measurement Results.....................................................................94
CHAPTER V CONCLUSIONS................................................................................100
APPENDIX I...................................................................................................................104
REFERENCES................................................................................................................156
v
LIST OF TABLES
1.1 SONET/SDH standard bit rates...............................................................................2
2.1 Relationships between BER, Q, and SNR.............................................................24
2.2 Cumulative power spectrum of NRZ signal..........................................................27
3.1 Required cell bandwidth for n-cascaded amplifier................................................54
3.2 Required cell gain for n-cascaded amplifier..........................................................54
5.1 Performance comparison of CMOS preamplifiers..............................................101

vi
LIST OF FIGURES
1.1 Diagram of generic optical communication system interface..................................3
2.1 Equivalent circuit model of photodetector...............................................................8
2.2 Power unit conversion graph.................................................................................11
2.3 Example of BER vs Sensitivity curve....................................................................13
2.4 Example of eye-diagram........................................................................................15
2.5 Example of pattern dependent jitter.......................................................................17
2.6 Example of pulse width distortion.........................................................................18
2.7 Probability of error of binary-coded signal............................................................22
2.8 Normalized power spectral density of NRZ signal................................................25
3.1 Block diagram of optical frontend.........................................................................29
3.2 Integrating amplifier..............................................................................................31
3.3 Common-gate preamplifier....................................................................................33
3.4 Two-stage feedback amplifier................................................................................36
3.5 Single-stage feedback amplifier.............................................................................37
3.6 Small signal models of single-ended and differential amplifier
including power supply inductances......................................................................40
3.7 Simplified schematic of optical frontend with noise sources................................46
3.8 Plot of normalized RMS noise vs normalized input capacitance..........................48
3.9 Transimpedance feedback amplifier using OP-Amp.............................................49
3.10 Transimpedance stage............................................................................................51
3.11 Cherry-Hooper amplifier.......................................................................................57
3.12 Capacitive peaking.................................................................................................59
3.13 Source degeneration...............................................................................................60
3.14 Shunt peaking.........................................................................................................62
3.15 Series peaking........................................................................................................64
3.16 Post amplifying stage.............................................................................................65
3.17 Output buffer..........................................................................................................69
4.1 Transimpedance gain curve using slow transistor corner model...........................71
4.2 Transimpedance gain curve using typical transistor corner model........................72
vii
4.3 Transimpedance gain curve using fast transistor corner model.............................72
4.4 Simulated eye-diagram using slow corner model operating at 5Gbit/s.................74
4.5 Simulated eye-diagram using typical corner model operating at 5Gbit/s..............75
4.6 Simulated eye-diagram using fast corner model operating at 5Gbit/s...................76
4.7 Simulated eye-diagram using slow corner model operating at 10Gbit/s...............77
4.8 Simulated eye-diagram using typical corner model operating at 10Gbit/s............78
4.9 Simulated eye-diagram using fast corner model operating at 10Gbit/s.................79
4.10 CMRR curves of circuit using slow, typical, and fast corner model.....................80
4.11 Noise simulation result using slow transistor corner model..................................82
4.12 Noise simulation result using typical transistor corner model...............................83
4.13 Noise simulation result using fast transistor corner model....................................84
4.14 Model of package line impedance.........................................................................85
4.15 Transient response without power supply decoupling capacitors..........................86
4.16 Transient response with power supply decoupling capacitors...............................87
4.17 Layout of preamplifier circuit................................................................................89
4.18 Photograph of preamplifier circuit with integrated I-MSM photodetector............92
4.19 Test board of integrated optical frontend circuit....................................................92
4.20 Measurement setup diagram..................................................................................93
4.21 Eye-diagram with 57uApp input photocurrent operating at 5Gbit/s.....................94
4.22 Eye-diagram with 113uApp input photocurrent operating at 5Gbit/s...................95
4.23 Eye-diagram with 57uApp input photocurrent operating at 10Gbit/s...................95
4.24 Eye-diagram with 113uApp input photocurrent operating at 10Gbit/s.................96
4.25 Eye-diagram with 57uApp input photocurrent operating at 5Gbit/s.....................97
4.26 Eye-diagram with 113uApp input photocurrent operating at 5Gbit/s...................97
4.27 Eye-diagram with 57uApp input photocurrent operating at 10Gbit/s...................98
4.28 Eye-diagram with 113uApp input photocurrent operating at 10Gbit/s.................98
4.29 Measured BER vs Input photocurrent....................................................................99
viii
SUMMARY
Trends toward increased integration and miniaturization of optical system
components have created pressure to consolidate widely disparate analog and digital
functions onto fewer and fewer chips with a goal of eventually built into a single mixed-
signal chip. Yet, because of those performance requirements, the frontend circuit has
traditionally used III-V compound semiconductor technologies, but the low-level of
integration with other digital ICs limits the sustainability of such end products for short-
distance applications. On the other hand, their CMOS counter parts, despite having such
advantages as low power consumption, high yield that lowers the cost of fabrication, and
a higher degree of integration, have not performed well enough to survive in such a noisy
environment without sacrificing other important attributes.
In this research, a high-speed CMOS preamplifier was designed and fabricated
through TSMC 0.18µm mixed-signal non-epi CMOS technology, and a 20µm diameter
InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a
wavelength of 1550µm was post-integrated onto the circuit. The circuit has a overall
transimpedance gain of 60dBΩ, and bit-error-rate data and eye-diagram measurement
results taken as high as 10Gbit/s are reported in this dissertation.
ix
CHAPTER I
INTRODUCTION

The advent of cheaper and more powerful personal computers has not only
expanded the user base but also created a demand for greater transmission capacity
among the telecom networks. In state-of-the-art technology, fiber optic devices and
systems are widely deployed to satisfy this need for more data throughput economically.
Fiber optic communication is an economic solution because its physical nature lets
network providers expand capacity either by increasing the transmission bit rate or by
introducing alternative transmission techniques. Neither alternative requires further
upgrades or additional cable installations [60-63].
In modern fiber optic transmission systems, the synchronous optical network
(SONET) and synchronous digital hierarchy (SDH) standard define a technology for
carrying many signals of different capacities through a synchronous, flexible, optical
hierarchy by means of a byte-interleaved multiplexing scheme [64-65]. The basic
transmission bit rate is OC-1 at 51.8Mbit/s, and higher bit rates offered by SONET/SDH
are summarized in Table 1.1. Furthermore, new techniques such as wavelength division
1