Table Of ContentMODELING AND SIMULATION OF
MIXED ANALOG-DIGITAL SYSTEMS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor
Mohammed Ismail
()hioState [Jniversi~
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MODELING AND SIMULATION OF
MIXED ANALOG-DIGITAL SYSTEMS
edited by
Brian Antao
Motorolla, Inc.
A Special Issue of
ANALOG INTEGRATED CIRCUITS
AND SIGNAL PROCESSING
An International Journal
Volume 10, No. 1/2 (1996)
KLUWER ACADEMIC PUBLISHERS
Boston / Dordrecht / London
Distributors for North America:
Kluwer Academic Publishers
10 1 Philip Drive
Assinippi Park
Norwell, Massachusetts 02061 USA
Distributors for all other countries:
Kll!wer Academic Publishers Group
Distribution Centre
Post Office Box 322
3300 AH Dordrecht, THE NETHERLANDS
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
ISBN-13: 978-1-4612-8609-7 e-ISBN-13: 978-1-4613-1405-9
DOl: 10.1007/978-1-4613-1405-9
Copyright © 1996 by Kluwer Academic Publishers
Softcover reprint of the hardcover 1st edition 1996
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park,
Norwell, Massachusetts 02061
Printed on acid-free paper.
Analog Integrated Circuits and Signal Processing, 10, 5-6 (1996)
© 1996 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Guest Editorial Introduction to the Special Issue
on Modeling and Simulation of Mixed and Analog-Digital Systems
Integrated circuit technology is perhaps one of the archical structure. This paper presents an interesting
fastest growing technology sectors, with rapid progress approach for exploring the feasibility and performance
being made in the design and fabrication processes. modeling of the various sub-blocks in a hierarchical
The design of more complex and increasingly dense design process. A vertical binary search technique is
designs continues at a frantic pace. Rapid scaling of used to generate feasibility macromodels and a layered
device sizes now enables complete systems to be inte- volume-slicing methodology with radial basis function
grated on chip. The newer generations of integrated cir- is used to generate the performance macromodel.
cuits are no longer purely analog or digital but include a Phase-locked 100ps(PLLs) are widely used in differ-
combination of different functionalities. Mixed signal ent applications, in purely digital form, mixed analog-
system design that largely combine analog and digital digital form, as well, as analog realizations. PLLs are
sections has also evolved into a field of its own to keep also recognized to be a class of circuits that are very
pace with this technology trend. We devote this special difficult to simulate, as they operate with largely vary-
issue to report on the leading-edge enabling develop- ing time-constants. The paper by B. Antao, F. El-Turky
ments in the modeling and simulation area, necessary and R. Leonowich describes the use of behavioral mod-
to support and fuel the mixed-signal design trend. In eling ofPLLs as a technique for making the simulation
this issue we have collected an excellent representa- and analysis of these circuits more tractable. These
tive set of papers that covers different aspects of this behavioral models can then be used in the simulation
area. of a larger system. They present examples of different
One of the key bottlenecks recognized in the design PLL configurations.
of mixed-signal integrated circuits as well as the newer Continuing in the line of behavioral modeling is
generation of other integrated circuits, is the model- the next paper by W. Kruiskamp and D. Leenaerts on
ing of the substrate. Noise that creeps from the high- behavioral and macromodeling using piecewise linear
activity digital sections tends to adversely affect the techniques. The authors advocate the use of piecewise
analog portions of a mixed signal chip. Hence efficient linear techniques as a consistent approach for modeling
modeling of the substrate is essential to account for components across the analog and digital boundaries.
the substrate induced effects early in the verification Emerging out of the efforts to find the ultimate pro-
phase. The first paper in this issue, by K. Kerns et al., cessing machine that can mimic some of the functional-
describes a novel approach for efficient modeling the ity of a human brain is a computational paradigm called
substrate. The authors use a non-rectangular substrate neural networks, based on the principles of biological
discretization method based on Vornoi tessellations and information processing systems. Early successes of
Delauney triangulation to generate mesh representa- these systems have been in various pattern recognition
tions of the substrate. They then apply a congruence tasks. In the next paper, the authors T. Wu, B. Sheu
transform based reduction to make the substrate mesh and E. Chou describe the behavioral modeling and sim-
representation more tractable for simulation. ulation techniques for such densely connected analog
The paper by R. Harjani and J. Shao describes cellular array processors, with pattern recognition ex-
feasibility and performance region macromodeling of amples.
analog-digital circuits. The use of hierarchy is im- We next digress a little and explore the use ofhierar-
portant in structuring the design of large mixed-signal chical modeling for fault simulation of analog circuits.
designs. As a design evolves through this hierarchical The design and realization of mixed-signal integrated
structure, we need various analyses and modeling tools circuits also raises the issue of testability and fault di-
that can be integrated into the design flow and address agnosis of these circuits. While there has been an enor-
the design issues that arise on account of this hier- mous amount of research on the digital side, the analog
6 Brian A. A. Antao
part of the equation is largely un-addressed, and this interact with a diverse range of people working in this
paper offers some perspectives. leading-edge field. There was a lot of interest and we
The paper by S. Donay et aI., "Using top-down CAD received an ample number of submissions. I would
tools for mixed analog/digital ASICs: A practical de- like to thank all the reviewers for their excellent and
sign case", presents a practical design case and serves detailed reviews of the various manuscripts, and their
as a unifying thread for the various approaches that have timely responses that enabled the prompt completion of
been presented, and how behavioral modeling and sim- this special issue. I would specially like to thank Car-
ulation is applied to the design process. This paper is olyn Genzel, the administrative assistant of the analog
an important demonstration on the use of the various and digital circuits group in the Coordinated Science
CAD techniques in a practical design case. Laboratory at the University of Illinois, for her efficient
In keeping up with the trends of large inter- handling of the manuscripts, and coordinating the re-
disciplinary system integration, electro-optical devices views. And finally, a special note of regrets to those
provide an additional set of challenges. This last pa- whose papers did not make it to this special issue for
per by V. Liberali, F. Maloberti and A. Regini, nicely various reasons, and hope it will not in any way dis-
rounds off the big picture and adds breadth by dis- courage you. I sincerely hope this special issue to be
cussing the modeling and simulation of electro-optical of great interest and benefit to the exciting integrated
devices. circuit design and CAD community at large.
As the guest editor, it was a sheer pleasure in com-
piling this special issue, giving me the opportunity to
Brian A. A. Antao,
Guest-Editor
Analog Integrated Circuits and Signal Processing, 10,7-21 (1996)
© 1996 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Efficient Parasitic Substrate Modeling for Monolithic
Mixed-AID Circuit Design and Verification
KEVIN J. KERNS, IVAN L. WEMPLE, AND ANDREW T. YANG, MEMBER, IEEE
Department of Electrical Engineering. University of Washington. Seattle, WA 98195
Abstract. Parasitic analog-digital noise coupling has been identified as a key issue facing designers of mixed-signal
integrated circuits. In particular, signal crosstalk through the common chip substrate has become increasingly
problematic. This paper demonstrates a methodology for developing simulation, synthesis, and verification models
to analyze the global electrical behavior of the non-ideal semiconductor substrate. First, a triangular discretization
method is employed to generate RC equivalent-circuit substrate models which are far less complex than those
formulated by conventional techniques. The networks are then accurately approximated for subsequent analysis
by an efficient reduction algorithm which uses a well-conditioned Lanczos moment-matching process. Through
congruence transformations, the network admittance matrices are transformed to reduced equivalents which are
easily post- processed to derive passive, SPICE-compatible netlist representations of the reduced models. The pure-
RC properties of the extracted substrate networks are fully exploited to formulate an efficient overall algorithm. For
validation, the strategy has been successfully applied to several mixed-signal circuit examples.
Introduction work in this area [3] used a box integration technique
to construct 3-D rectangular RC mesh networks as
Industry trends aimed at integrating higher levels of cir- equivalent circuit representations of the modeled sub-
cuit functionality have triggered a proliferation of ana- strates. The mesh topology could be correlated to the
log and digital subsystems fabricated side-by-side on circuit's physical design by distributing grid points ac-
the same die. The combined requirements for both high cording to the layout features on relevant fabrication
speed digital and high precision analog circuitry pro- photomasks [4]. Unfortunately, layout-driven rectan-
duce unique challenges to mixed-AID circuit design- gular grid generation is prone to substrate "overparti-
ers. Specifically, monolithic mixed-signal ICs are often tioning", which yields unnecessarily dense grid crowd-
characterized by parasitic analog-digital interactions ing in many regions of the chip. The strategy produces
which can cripple the operation of high-performance enormous circuit networks, even for moderately sized
designs. Noise coupling through the common chip sub- layouts. Since a primary objective of equivalent cir-
strate has been identified as a significant contributor to cuit macromodeling is to build simulation-ready net-
this important problem [1], [2]. works, the inordinate complexity of the generated mod-
Modeling the electrical behavior of non-ideal semi- els is self-defeating-subsequent simulation on con-
conductor substrates is of key interest to the mixed- ventional CAD workstations becomes virtually impos-
signal design community. For state-of-the-art circuits, sible.
chip-level verification which excludes the effects of To address the complexity issues, intermediate pro-
substrate coupling may be of questionable validity. As cessing is required to approximate the generated linear
a result, substrate modeling for circuit simulation has RC networks by smaller circuits which exhibit simi-
been the focus of much research in recent years. Early lar electrical properties. Since a typical mesh is dense
8 K. 1. Kerns, I. L. Wemple, and A. T. Yang
and three-dimensional, only a small percentage of net- generation and network reduction levels. For ini-
work nodes, called ports, are physically connected to tial mesh generation, a well-known geometric con-
the external circuit (at the top surface of the modeled struct can be efficiently applied to overcome the single
substrate). In theory, an "equivalent" network can be most important drawback of rectangular mesh formu-
formulated by eliminating a substantial fraction of the lation methods-that is, localized mesh refinement, of-
internal nodes. The resulting network is appropriate ten required in regions of dense switching activity, is
for simulation if its port characteristics remain consis- propagated to distant layout regions where a coarser
tent with those of the original mesh. This technique is mesh might otherwise be adequate. By using a non-
generally referred to as network reduction. rectangular gridding method, we extract a mesh which
To accurately accommodate general, lumped- automatically and locally adjusts itself to the density
element substrate models, Asymptotic Waveform Eval- of substrate features as inferred from the layout speci-
uation (AWE) [5] has been proposed as a method to re- fication. Mesh extraction based on this approach gen-
duce mesh networks for mixed-signal switching noise erates substrate circuit networks containing orders of
analysis [6]. The AWE algorithm approximates a net- magnitude fewer circuit nodes than those of conven-
work's multiport behavior by recursively calculating tional gridding techniques. A brief description of the
the moments of the port characteristics and then fit- substrate model formulation, first presented in [8], is
ting these moments to pole-residue functions via the provided in Section II.
Pade approximation. A well-known problem with this In spite of the improved model generation technique,
technique is that calculation of the higher moments is extracted full-chip substrate networks still promise to
inherently ill-conditioned-increasing the number of be exceedingly complex. For model reduction, we
poles used to model a given network does not guar- demonstrate a new multiport algorithm which fully
antee a better approximation. Heuristic methods have exploits the pure-RC property of our formulated net-
been developed to address this issue (e.g., see the ref- works and directly generates reduced equivalent circuit
erences in [7]), but only at the cost of increased com- models in a well-conditioned manner. Using congru-
putational complexity. Another problem with AWE ence transformations, full-network conductance and
relates to the stability of the network approximation. susceptance matrices are transformed to reduced equiv-
While asymptotic stability is maintained by eliminating alents which can be directly realized with resistors and
positive poles, absolute stability is not easily ensured. capacitors. The approximated networks are guaran-
Consequently, non-physical, artificial oscillations may teed to be passive, and thus well-behaved in subsequent
appear during subsequent transient simulations. simulations. Proper formulation of the transformation
Network models detailed enough to accurately pre- ensures that the networks possess a minimal number of
dict the chip-level impact of substrate coupling are, by internal nodes and branches, and yield a specified ac-
necessity, very complex. It is not surprising that tangi- curacy from DC to a specified maximum frequency of
ble simulation results have been obtained only for small interest. The requisite transforms are generated using a
device-scale examples, as existing methods possess in- symmetric Lanczos method which exploits the special-
herent limitations which render them impractical for ized structure of the extracted substrate networks. Re-
circuits of reasonable size. The mixed-signal design quired matrix inversions are performed using efficient
process can be greatly enhanced by the development methods which also profit from the problem symmetry.
of software tools which can efficiently extract accurate Since matrix inversion often accounts for a substan-
chip-level simulation substrate models directly from tial network reduction bottleneck, this strategy can be
a physical design specification. Reliable verification significantly faster than general AWE methods, which
of circuit functionality obviously reduces the length of employ nonsymmetric techniques. Section III provides
the overall design cycle and promotes the likelihood of the theoretical details and an implementation descrip-
first-time silicon success. Perhaps more importantly, tion of the proposed substrate model network reduc-
robust new noise reduction techniques can be devel- tion methodology. The non-rectangular gridding strat-
oped more rapidly if capabilities exist to accurately egy and the congruence-transformation-based network
assess and analyze the impact of switching noise in reduction algorithm combine to form a unified, effi-
proposed design methodologies. cient strategy for developing parasitic substrate models
We propose a substrate modeling strategy which ad- for mixed-signal circuit simulation and design verifica-
dresses the mesh complexity issue at both the model tion. The overall approach has been applied to several
Efficient Parasitic Substrate Modeling for Monolithic Mixed-AID Circuit Design and Verification 9
mixed-signal design examples, which we present in the plane to the closest member in the set of point sites.
Section IV. As a result, the locations associated with each mem-
ber form a convex polygon. Together, the polygons
partition the substrate surface into a non-overlapping,
Model Extraction Using Non-Rectangular Sub-
collectively exhaustive set of regions called the Voronoi
strate Discretization
diagram, a portion of which is shown in Fig. lb.
A popular and physically-based approach to parasitic Connecting each pair of sites that share a common
substrate modeling employs an equivalent circuit mesh edge in the Voronoi diagram is known as Delaunay tri-
representation of the modeled substrate [3], [4], [6], angulation (Fig. Ic). For reasons we discuss below,
[9]. A common drawback of previously reported mod- a key property of the triangulation is that each edge
eling strategies, however, is that the derived networks connecting adjacent sites is perpendicular to the com-
ultimately contain circuit nodes in substrate regions mon Voronoi polygon boundary between the sites. The
where they are not required to obtain accurate simula- line segments which constitute the triangulation can
tion results. As emphasized in our introduction, sub- be used as a basis for the branch topology of a rep-
resentative electrical network. Assuming for now we
sequent mesh processing typically involves network
reduction, and, ultimately, simulation. Since the com- wish to model the resistive properties of the substrate,
the triangulation-based network topology is shown in
putational efficiency of these procedures is directly im-
pacted by the complexity of the generated network, it is Fig. Id.
of enormous advantage to constrain the size of the orig- In actuality, the substrate properties are not homoge-
neous, and a two-dimensional network model (like that
inal mesh by adopting efficient techniques for model
extraction. For mesh generation, we employ a non- shown in Fig. 1) is not adequate to capture the electri-
cal behavior of the modeled substrate. To account for
rectangular substrate discretization based on geomet-
doping non-uniformities, the mesh is extended to three
ric constructs known as the Voronoi tessellation and the
Delaunay triangulation [10]. The derived mesh effi- dimensions by stacking structurally identical, triangu-
lated (x, y) planes on top of one another, and intercon-
ciently conforms to the substrate feature topology as
necting them site-to-site using appropriately-valued in-
dictated by the physical layout of the circuit. This sec-
tion summarizes our modeling approach. For greater terplane branch circuit elements. Owing to the one-
detail, the reader is referred to [8]. to-one correspondence between tessellation sites and
network circuit nodes, each (x, y) plane is termed a
The network formulation strategy is based on the
nodeplane.
observation that typical ICs contain areas of intricate
Excepting those regions which comprise the well
complexity surrounded by comparatively large regions
boundaries (e.g., in CMOS circuits), linear resistors
with little structural detail. In gate array, standard-cell,
and most custom designs, large chip areas contain no typically suffice for modeling the bulk electrical prop-
erties of the substrate [4]. To accommodate the de-
active devices but are dedicated to routing channels.
pletion capacitance associated with the well junctions,
Since transistors and contacts are the primary sources
special tessellation sites are introduced in pairs which
and collectors of noise current, it makes sense to parti-
tion the chip according to the "localized" densities of straddle the well boundaries. If adjacent pairs are prop-
erly spaced, the corresponding triangulation segments
relevant substrate features.
are always perpendicular to the well edges, and mod-
Our approach is demonstrated qualitatively in Fig. 1,
which shows a mixed-signal circuit and a progression eling the junction capacitance is simplified.
The model extraction combines substrate technol-
of illustrations depicting the sequence of procedures
used to discretize the underlying substrate. During lay- ogy data and the geometries of the individual Voronoi
out extraction, polygons representing relevant substrate polygons and associated triangulation edges to derive
features are converted to equivalent internal point rep- the values of the linear resistors and capacitors which
resentations. In Fig. la, for example, derived layout comprise the network. To demonstrate the procedure
information from the chip inset yields point locations for determining the resistor values, we refer to the por-
for the enclosed transistors and substrate tie-downs. tion of the arbitrary triangulation shown in Fig. 2. The
Voronoi tessellation is the procedure we use to sub- tessellation sites i and j represent circuit nodes, and
divide the Euclidean plane according to the distribution polygons Pi and Pj are the Voronoi polygons enclos-
of point sites. The tessellation assigns every location in ing each site. Our objective is to formulate a resistance,
10 K. 1. Kerns, I. L. Wemple, and A. T. Yang
(a)
(b)
(e)
(d)
Fig. 1. Overview of the non-rectangular substrate discretization strategy applied to a mixed-signal IC. The insets show (a) site representations of
the layout -derived substrate features, (b) the corresponding Voronoi tessellation, (c) the Delaunay triangulation, and (d) the resultant electrical
network topology.
R;j' which models the network branch between nodes The resistor current is the normal flux crossing the poly-
i and j. The voltage drop between the nodes is the line gon edge common to Pi and Pj , segment ab:
integral of the electric field, E, between i and j, i.e.,
Vi - V; = - [i E . dl. (1) (2)
