LTC2440 - 24-Bit High Speed Differential Delta Sigma ADC with

28 Pages·2008·0.35 MB·English

by  Linear Technology Corporation

LTC2440
24-Bit High Speed
Differential Δ∑ ADC with
Selectable Speed/Resolution
FEATURES DESCRIPTION
n Up to 3.5kHz Output Rate The LTC®2440 is a high speed 24-bit No Latency Δ∑TM
n Selectable Speed/Resolution ADC with 5ppm INL and 5μV offset. It uses proprietary
n 2μV Noise at 880Hz Output Rate delta-sigma architecture enabling variable speed and reso-
RMS
n 200nV Noise at 6.9Hz Output Rate with lution with no latency. Ten speed/resolution combinations
RMS
Simultaneous 50/60Hz Rejection (6.9Hz/200nV to 3.5kHz/25μV ) are programmed
RMS RMS
n 0.0005% INL, No Missing Codes through a simple serial interface. Alternatively, by tying a
n Autosleep Enables 20μA Operation at 6.9Hz single pin HIGH or LOW, a fast (880Hz/2μV ) or ultralow
RMS
n <5μV Offset (4.5V < V < 5.5V, –40°C to 85°C) noise (6.9Hz, 200nV , 50/60Hz rejection) speed/reso-
CC RMS
n Differential Input and Differential Reference with lution combination can be easily selected. The accuracy
GND to V Common Mode Range (offset, full-scale, linearity, drift) and power dissipation
CC
n No Latency, Each Conversion is Accurate Even After are independent of the speed selected. Since there is no
an Input Step latency, a speed/resolution change may be made between
n Internal Oscillator—No External Components conversions with no degradation in performance.
n Pin Compatible with the LTC2410
Following each conversion cycle, the LTC2440 automati-
n 24-Bit ADC in Narrow 16-Lead SSOP Package
cally enters a low power sleep state. Power dissipation
may be reduced by increasing the duration of this sleep
APPLICATIONS
state. For example, running at the 3.5kHz conversion speed
but reading data at a 100Hz rate draws 240μA average
n High Speed Multiplexing
current (1.1mW) while reading data at a 7Hz output rate
n Weight Scales
draws only 25μA (125μW).The LTC2440 communicates
n Auto Ranging 6-Digit DVMs
through a fl exible 3-wire or 4-wire digital interface that is
n Direct Temperature Measurement
compatible with the LTC2410 and is available in a narrow
n High Speed Data Acquisition
16-lead SSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency Δ∑ is a trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
TYPICAL APPLICATION
Speed vs RMS Noise
Simple 24-Bit 2-Speed Acquisition System 100
VCC = 5V
VREF = 5V
4.5V TO 5.5V VIN+ = VIN– = 0V
VCC BUSY μV) 10
LTC2440 SE ( 2μV AT 880Hz
REFERENCE VOLTAGE REF+ fO NOI
0.1V TO VCC 4 REF– SCK MS 200nV AT 6.9Hz
ANALOG INPUT IN+ SDO 3S-PWI IINRTEERFACE VCC6.9Hz, 200nV NOISE, R 1 (50/60Hz REJECTION)
–0.5VREF TO 0.5VREF IN– CS 50/60Hz REJECTION
10-SPEED SERIAL
SDI PROGRAMMABLE
0.1
GND EXT 880Hz OUTPUT RATE, 1 10 100 1000 10000
2μV NOISE CONVERSION RATE (Hz)
2440 TA01
2440 TA01
2440 TA02
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LTC2440
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Notes 1,2)
Supply Voltage (VCC) to GND .......................–0.3V to 6V TOP VIEW
Analog Input Pins Voltage
GND 1 16 GND
to GND ......................................–0.3V to (V + 0.3V)
CC VCC 2 15 BUSY
Reference Input Pins Voltage REF+ 3 14 fO
to GND ......................................–0.3V to (VCC + 0.3V) REF– 4 13 SCK
Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V) IN+ 5 12 SDO
Digital Output Voltage to GND .......–0.3V to (V + 0.3V) IN– 6 11 CS
CC
Operating Temperature Range SDI 7 10 EXT
LTC2440C ...............................................0°C to 70°C GND 8 9 GND
LTC2440I .............................................–40°C to 85°C GN PACKAGE
16-LEAD PLASTIC SSOP
Storage Temperature Range ...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C TJMAX = 125°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2440CGN#PBF LTC2440CGN#TRPBF 2440 Narrow 16-Lead SSOP 0°C to 70°C
LTC2440IGN#PBF LTC2440IGN#TRPBF 2440I Narrow 16-Lead SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T = 25°C. (Notes 3, 4)
A
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5) l 24 Bits
REF CC REF IN REF
Integral Nonlinearity V = 5V, REF+ = 5V, REF– = GND, V = 2.5V, (Note 6) l 5 15 ppm of V
CC INCM REF
REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 3 ppm of V
INCM REF
Offset Error 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN+ = IN– ≤ V (Note 12) l 2.5 5 μV
CC CC
Offset Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN+ = IN– ≤ V 20 nV/°C
CC CC
Positive Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25V l 10 30 ppm of V
REF
REF+ = 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V l 10 50 ppm of V
REF
Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ 0.2 ppm of V /°C
CC REF
Negative Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75V l 10 30 ppm of V
REF
REF+ = 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V l 10 50 ppm of V
REF
Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 0.2 ppm of V /°C
CC REF
Total Unadjusted Error 5V ≤ V ≤ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V 15 ppm of V
CC INCM REF
5V ≤ V ≤ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V 15 ppm of V
CC INCM REF
REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 15 ppm of V
INCM REF
Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN– = IN+ ≤ V 120 dB
CC CC
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LTC2440
ANALOG INPUT AND REFERENCE
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T = 25°C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3V V + 0.3V V
CC
IN– Absolute/Common Mode IN– Voltage l GND – 0.3V V + 0.3V V
CC
V Input Differential Voltage Range (IN+ – IN–) l –V /2 V /2 V
IN REF REF
REF+ Absolute/Common Mode REF+ Voltage l 0.1 V V
CC
REF– Absolute/Common Mode REF– Voltage l GND V – 0.1V V
CC
V Reference Differential Voltage Range (REF+ l 0.1 V V
REF CC
– REF–)
CS(IN+) IN+ Sampling Capacitance 3.5 pF
CS(IN–) IN– Sampling Capacitance 3.5 pF
CS(REF+) REF+ Sampling Capacitance 3.5 pF
CS(REF–) REF– Sampling Capacitance 3.5 pF
IDC_LEAK(IN+, IN–, Leakage Current, Inputs and Reference CS = VCC, IN+ = GND, IN– = GND, l –100 10 100 nA
REF+, REF–) REF+ = 5V, REF– = GND
ISAMPLE(IN+, IN–, Average Input/Reference Current During Varies, See Applications Section
REF+, REF–) Sampling
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at T = 25°C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V High Level Input Voltage 4.5V ≤ V ≤ 5.5V l 2.5 V
IN CC
CS, f , SDI
O
V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V l 0.8 V
IL CC
CS, f , SDI
O
V High Level Input Voltage 4.5V ≤ V ≤ 5.5V (Note 8) l 2.5 V
IN CC
SCK
V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V (Note 8) l 0.8 V
IL CC
SCK
I Digital Input Current 0V ≤ V ≤ V l –10 10 μA
IN IN CC
CS, f
O
I Digital Input Current 0V ≤ V ≤ V (Note 8) l –10 10 μA
IN IN CC
SCK
C Digital Input Capacitance 10 pF
IN
CS, f
O
C Digital Input Capacitance (Note 8) 10 pF
IN
SCK
V High Level Output Voltage I = –800μA l V – 0.5V V
OH O CC
SDO, BUSY
V Low Level Output Voltage I = 1.6mA l 0.4V V
OL O
SDO, BUSY
V High Level Output Voltage I = –800μA (Note 9) l V – 0.5V V
OH O CC
SCK
V Low Level Output Voltage I = 1.6mA (Note 9) l 0.4V V
OL O
SCK
I Hi-Z Output Leakage l –10 10 μA
OZ
SDO
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LTC2440
POWER REQUIREMENTS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T = 25°C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V Supply Voltage l 4.5 5.5 V
CC
ICC Supply Current
Conversion Mode CS = 0V (Note 7) l 8 11 mA
Sleep Mode CS = V (Note 7) l 8 30 μA
CC
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T = 25°C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f External Oscillator Frequency Range l 0.1 20 MHz
EOSC
t External Oscillator High Period l 25 10000 ns
HEO
t External Oscillator Low Period l 25 10000 ns
LEO
t Conversion Time OSR = 256 (SDI = 0) l 0.99 1.13 1.33 ms
CONV
OSR = 32768 (SDI = 1) l 126 145 170 ms
l
40 • OSR + 170
External Oscillator (Note 10, 13) ms
f (kHz)
EOSC
f Internal SCK Frequency Internal Oscillator (Note 9) l 0.8 0.9 1
ISCK
External Oscillator (Notes 9, 10) fEOSC/10
D Internal SCK Duty Cycle (Note 9) l 45 55 %
ISCK
f External SCK Frequency Range (Note 8) l 20 MHz
ESCK
t External SCK Low Period (Note 8) l 25 ns
LESCK
t External SCK High Period (Note 8) l 25 ns
HESCK
t Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 30.9 35.3 41.6 μs
DOUT_ISCK
External Oscillator (Notes 9, 10) 320/fEOSC s
t External SCK 32-Bit Data Output Time (Note 8) l 32/f s
DOUT_ESCK ESCK
t CS ↑ to SDO Low Z (Note 12) l 0 25 ns
1
t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns
t CS ↑ to SCK↑ (Note 9) l 5 μs
3
t4 CS ↑ to SCK ↑ (Notes 8, 12) l 25 ns
t SCK ↑ to SDO Valid l 25 ns
KQMAX
t SDO Hold After SCK ↑ (Note 5) l 15 ns
KQMIN
t SCK Set-Up Before CS ↑ l 50 ns
5
t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns
t8 SDI Hold After SCK ↑ (Note 5) l 10 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may Note 7: The converter uses the internal oscillator.
cause permanent damage to the device. Exposure to any Absolute Maximum Note 8: The converter is in external SCK mode of operation such that the
Rating condition for extended periods may affect device reliability and lifetime. SCK pin is used as a digital input. The frequency of the clock signal driving
Note 2: All voltage values are with respect to GND. SCK during the data output is f and is expressed in Hz.
ESCK
Note 3: V = 4.5 to 5.5V unless otherwise specifi ed. Note 9: The converter is in internal SCK mode of operation such that the
CC
V = REF+ – REF–, V = (REF+ + REF–)/2; SCK pin is used as a digital output. In this mode of operation, the SCK pin
REF REFCM
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. has a total equivalent load capacitance of CLOAD = 20pF.
Note 4: fO pin tied to GND or to external conversion clock source with Note 10: The external oscillator is connected to the fO pin. The external
fEOSC = 10MHz unless otherwise specifi ed. oscillator frequency, fEOSC, is expressed in kHz.
Note 5: Guaranteed by design, not subject to test. Note 11: The converter uses the internal oscillator. fO = 0V.
Note 6: Integral nonlinearity is defi ned as the deviation of a code from a Note 12: Guaranteed by design and test correlation.
straight line passing through the actual endpoints of the transfer curve. Note 13: There is an internal reset that adds an additional 1μs (typical) to
The deviation is measured from the center of the quantization band. the conversion time.
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LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
Integral Nonlinearity f = 3.5kHz f = 1.76kHz Integral Nonlinearity f = 880Hz
OUT OUT OUT
10 10 10
VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V
OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC
m m m
R (pp 0 R (pp 0 R (pp 0
O O O
R R R
R R R
NL E –5 NL E –5 NL E –5
I I I
–10 –10 –10
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
VIN (V) VIN (V) VIN (V)
2440 G01 2440 G02 2440 G03
Integral Nonlinearity f = 440Hz Integral Nonlinearity f = 220Hz Integral Nonlinearity f = 110Hz
OUT OUT OUT
10 10 10
VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V
OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC
m m m
R (pp 0 R (pp 0 R (pp 0
O O O
R R R
R R R
NL E –5 NL E –5 NL E –5
I I I
–10 –10 –10
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
VIN (V) VIN (V) VIN (V)
2440 G04 2440 G05 2440 G06
Integral Nonlinearity
Integral Nonlinearity f = 55Hz Integral Nonlinearity f = 27.5Hz f = 13.75Hz
OUT OUT OUT
10 10 10
VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V
m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC
INL ERROR (pp –50 INL ERROR (pp –50 INL ERROR (pp –50
–10 –10 –10
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
VIN (V) VIN (V) VIN (V)
2440 G07 2440 G08 2440 G09
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LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity Integral Nonlinearity
f = 6.875Hz vs Conversion Rate Integral Nonlinearity vs V
OUT INCM
10 10.0 10
VCC = 5V VINCM = 2.5V VCC = 5V –2.5V ≤ VIN ≤ 2.5V
VREF = 5V fO = GND VREF = 5V VINCM = 2.5V
VREF+ = 5V TA = 25°C VREF+ = 5V fO = GND VINCM = 3.75V
OF V)REF 5 VREF– = GND OF V)REF7.5 VREF– = GND TA = 25°C OF V)REF 5 VINCM = 2.5V
m m m
pp 0 pp 5.0 pp 0
R ( R ( R (
O O O
R R R VINCM = 1.25V
R R R
E E E
INL –5 INL 2.5 INL –5 VCC = 5V OSR = 32768
VREF = 2.5V fO = GND
VREF+ = 2.5V TA = 25°C
VREF– = GND
–10 0 –10
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 0 500 1000 1500 2000 2500 3000 3500 –1.25 –0.75 –0.25 0.25 0.75 1.25
VIN (V) CONVERSION RATE (Hz) VIN (V)
2440 G10 2440 G11 2440 G12
Integral Nonlinearity Integral Nonlinearity
vs Temperature vs Temperature –Full-Scale Error vs V
REF
10 10 20
VCC = 5V VINCM = 1.25V VCC = 5V VINCM = 2.5V
INL ERROR (ppm OF V)REF –505 VVVRRREEEFFF +–T= ==A T2 A2G=.5 . N=5–V DV5255°°CCOfOS =R GT=NA 3 D=2 716285°C INL ERROR (ppm OF V)REF –505 VVVRRREEEFFF +–T= A== 5 T=5GVA VN– =2D 51°2COf5O°S C=R G=N 3D2T7A6 8= 25°C LL-SCALE ERROR (ppm OF V)REF–11000
U
F
–
–10 –10 –20
–1.25 –0.75 –0.25 0.25 0.75 1.25 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5
VIN (V) VIN (V) VREF (V)
2440 G13 2440 G14 2440 G15
+Full-Scale Error vs V –Full-Scale Error vs V +Full-Scale Error vs V
REF CC CC
20 10 0
VREF = 2.5V OSR = 32768
m OF V)REF 10 m OF V)REF 879 m OF V)REF –––231 VVVRRINEECFFM+– === 2G1.N.52DV5V TfOA == G2N5°DC
R (pp R (pp 6 R (pp –4
RO 0 RO 5 RO –5
R R R
+FULL-SCALE E –10 FULL-SCALE E 4231 VVVRRREEEFFF +–= == 2 2G.5.N5VDV TOfOAS =R= G2=N5 3°D2C768 FULL-SCALE E ––––6879
VINCM = 1.25V
–20 0 –10
0 1 2 3 4 5 4.5 4.7 4.9 5.1 5.3 5.5 4.5 4.7 4.9 5.1 5.3 5.5
VREF (V) VCC (V) VCC (V)
2440 G16 2440 G17 2440 G18
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LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Full-Scale Error Positive Full-Scale Error
vs Temperature vs Temperature Offset Error vs V
CC
20 20 5.0
VCC = 4.5V VCC = 5.5V, 5V VREF = 2.5V OSR = 32768
R (ppm OF V)REF 11505 4.5V VVVVOfORRRISN =EEERCFFF MG +–== N == =34D 24G.257.N.5V26DV58V VVVVOfORRRISN =EEERCFFF MG +–== N == =35D 25GV27VN.56DV8 R (ppm OF V)REF 11505 5.5V ppm OF V)REF 2.5 VVVRRINEE+FF +–= ==V I2GN.N–5 DV= GND TfOA == G2N5°DC
RO 0 RO 0 R ( 0
LE ER –5 5.5V LE ER –5 5V VVCRCEF = = 4 4.5.5VV VVCRCEF = = 5 5.5VV, 5V ERRO
ULL-SCA –10 5V ULL-SCA –10 4.5V VVVRRINEECFFM+– === 4G2.N.52DV5V VVVRRINEECFFM+– === 5G2VN.5DV OFFSET –2.5
F –15 F –15 OSR = 32768 OSR = 32768
fO = GND fO = GND
–20 –20 –5.0
–55 –25 5 35 65 95 125 –55 –25 5 35 65 95 125 4.5 4.7 4.9 5.1 5.3 5.5
TEMPERATURE (°C) TEMPERATURE (°C) VCC (V)
2440 G19 2440 G20 2440 G21
Offset Error vs Conversion Rate Offset Error vs V RMS Noise vs Temperature
INCM
5.0 VCC = 5V VIN+ = VIN– = GND 5.0 VCC = 5V VIN+ = VIN– = VINCM 3.5
R (ppm OF V)REF2.50 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC R (ppm OF V)REF 2.05 VVVRRREEEFFF +–= == 5 5GVVND TOfOAS =R= G2=N5 3°D2C768 OISE (μV) 322...005 VVVCCCCCC === 545..V55VV
O O N
OFFSET ERR–2.5 OFFSET ERR–2.5 RMS 11..05 VVVVVCRRRINCEEE+FFF = +–== 4== V2. 5I2G.N5V.N–5V DV= GND VVVVVCRRRINCEEE+FFF = +–== 5== V5. 5I5GVNVVN–, D =5 VGND
OSR = 256 OSR = 256
–5.0 –5.0 0.5 fO = GND fO = GND
0 500 1000 1500 2000 2500 3000 3500 0 1 2 3 4 5 –55 –25 5 35 65 95 125
CONVERSION RATE (Hz) VINCM (V) TEMPERATURE (°C)
2440 G22 2440 G23 2440 G24
INL vs Output Rate RMS Noise vs Output Rate
(OSR = 128) External Clock Sweep (OSR = 128) External Clock
Offset Error vs Temperature 10MHz to 20MHz Sweep 10MHz to 20MHz
5.0 20 5
18
16 4
2.5
OFFSET ERROR (μV)–2.50 VCC = 5VVVVVVCRRRINCEEE+FFF = +–== V 4== V2.C 5I2G.CN5V.N –5V= DV= 5 G.5NVD VVVVVVCRRRICNCEEEC+FFF == +–== 5==4 V5. .5I5G5VNVVVN–, D =5 VGND LINEARITY (BITS) 111420864 E(OXVTRTER EMEIRFNP NT= =E AV RL2CN 5CC°A L=CLO 5 OCVKS C1I0LMLAHTzOR)ECXLTOECRKN 2A0LMHz RMS NOISE (μV) 321 VTERMEFP = = V 2C5C° =C 5V
OSR = 256 OSR = 256 2 SWEEP (VIN – VREF/2) TO VREF/2 VIN ±VREF/2
–5.0 fO = GND fO = GND 0 0
–55 –25 5 35 65 95 125 2000 2500 3000 3500 4000 2000 2500 3000 3500 4000
TEMPERATURE (°C) OUTPUT RATE (Hz) OUTPUT RATE (Hz)
2440 G25 2440 G26 2440 G27
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LTC2440
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins is selected. The device generates its own SCK signal and
internally connected for optimum ground current fl ow and outputs this on the SCK pin. A framing signal BUSY (Pin 15)
V decoupling. Connect each one of these pins to a ground goes low indicating data is being output.
CC
plane through a low impedance connection. All four pins
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
must be connected to ground for proper operation.
enables the SDO digital output and wakes up the ADC.
V (Pin 2): Positive Supply Voltage. Bypass to GND Following each conversion the ADC automatically enters
CC
(Pin 1) with a 10μF tantalum capacitor in parallel with 0.1μF the Sleep mode and remains in this low power state as
ceramic capacitor as close to the part as possible. long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
and starts a new conversion.
The voltage on these pins can have any value between
GND and V as long as the reference positive input, REF+, SDO (Pin 12): Three-State Digital Output. During the Data
CC
is maintained more positive than the reference negative Output period, this pin is used as serial data output. When
input, REF–, by at least 0.1V. the chip select CS is HIGH (CS = V ) the SDO pin is in a
CC
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output. The
voltage on these pins can have any value between GND
conversion status can be observed by pulling CS LOW.
– 0.3V and V + 0.3V. Within these limits the converter
CC
bipolar input range (VIN = IN+ – IN–) extends from –0.5 SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
• (VREF) to 0.5 • (VREF). Outside this input range the Serial Clock Operation mode, SCK is used as digital output
converter produces unique overrange and underrange for the internal serial interface clock during the Data Output
output codes. period. In External Serial Clock Operation mode, SCK is used
as digital input for the external serial interface clock during
SDI (Pin 7): Serial Data Input. This pin is used to select
the Data Output period. The Serial Clock Operation mode is
the speed/resolution of the converter. If SDI is grounded
determined by the logic level applied to the EXT pin.
(pin compatible with LTC2410) the device outputs data at
880Hz with 21 bits effective resolution. By tying SDI HIGH, f (Pin 14): Frequency Control Pin. Digital input that con-
O
the converter enters the ultralow noise mode (200nVRMS) trols the internal conversion clock. When fO is connected to
with simultaneous 50/60Hz rejection at 6.9Hz output
V or GND, the converter uses its internal oscillator running
CC
rate. SDI may be driven logic HIGH or LOW anytime dur-
at 9MHz. The conversion rate is determined by the selected
ing the conversion or sleep state in order to change the
OSR such that t (in ms) = (40 • OSR + 170)/9000
CONV
speed/resolution. The conversion immediately following
(t = 1.137ms at OSR = 256, t = 146ms at OSR =
CONV CONV
the data output cycle will be valid and performed at the
32768). The fi rst null is located at 8/t , 7kHz at OSR =
CONV
newly selected output rate/resolution. SDI may also be
256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768.
programmed by a serial input data stream under control of
SCK during the data output cycle. One of ten speed/resolu- When fO is driven by an oscillator with frequency fEOSC (in
tion ranges (from 6.9Hz/200nVRMS to 3.5kHz/21μVRMS) kHz), the conversion time becomes tCONV = (40 • OSR +
may be selected. The fi rst conversion following a new 170)/fEOSC (in ms) and the fi rst null remains 8/tCONV.
selection is valid and performed at the newly selected
BUSY (Pin 15): Conversion in Progress Indicator. For
speed/resolution.
compatibility with the LTC2410, this pin should not be
EXT (Pin 10): Internal/External SCK Selection Pin. This pin tied to ground. This pin is HIGH while the conversion
is used to select internal or external SCK for outputting is in progress and goes LOW indicating the conversion
data. If EXT is tied low (pin compatible with the LTC2410), is complete and data is ready. It remains low during the
the device is in the external SCK mode and data is shifted sleep and data output states. At the conclusion of the data
out the device under the control of a user applied serial output state, it goes HIGH indicating a new conversion
clock. If EXT is tied high, the internal serial clock mode has begun.
2440fd
8
LTC2440
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
VCC OSCILLATOR
GND AUTOCALIBRATION
AND CONTROL fO
(INT/EXT)
IN+ +
IN– –
SDO
ADC SCK
SERIAL CS
DECIMATING FIR INTERFACE
SDI
BUSY
DAC 2440 F01
EXT
+ –
REF+
REF–
Figure 1. Functional Block Diagram
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOH
VVOOLH TTOO VHOi-HZ 2440 TA03 HVOi-HZ TTOO VVOOLL
VOL TO Hi-Z 2440 TA04
APPLICATIONS INFORMATION
CONVERTER OPERATION
CONVERT
Converter Operation Cycle
The LTC2440 is a high speed, delta-sigma analog-to-digital
SLEEP
converter with an easy to use 4-wire serial interface (see
Figure 1). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
FALSE CS = LOW
followed by the low power sleep state and ends with the AND
SCK
data output (see Figure 2). The 4-wire interface consists
of serial data input (SDI), serial data output (SDO), serial TRUE
clock (SCK) and chip select (CS). The interface, timing,
DATA OUTPUT
operation cycle and data out format is compatible with
2440 F02
the LTC2410.
Figure 2. LTC2440 State Transition Diagram
2440fd
9
LTC2440
APPLICATIONS INFORMATION
Initially, the LTC2440 performs a conversion. Once the Power-Up Sequence
conversion is complete, the device enters the sleep state.
The LTC2440 automatically enters an internal reset state
While in this sleep state, power consumption is reduced
when the power supply voltage V drops below ap-
CC
below 10μA. The part remains in the sleep state as long
proximately 2.2V. This feature guarantees the integrity
as CS is HIGH. The conversion result is held indefi nitely
of the conversion result and of the serial interface mode
in a static shift register while the converter is in the sleep
selection.
state.
When the V voltage rises above this critical threshold, the
CC
Once CS is pulled LOW, the device begins outputting the
converter creates an internal power-on-reset (POR) signal
conversion result. There is no latency in the conversion
with a duration of approximately 0.5ms. The POR signal
result. The data output corresponds to the conversion
clears all internal registers. Following the POR signal, the
just performed. This result is shifted out on the serial data
LTC2440 starts a normal conversion cycle and follows the
out pin (SDO) under the control of the serial clock (SCK).
succession of states described above. The fi rst conversion
Data is updated on the falling edge of SCK allowing the
result following POR is accurate within the specifi cations
user to reliably latch data on the rising edge of SCK (see
of the device if the power supply voltage is restored within
Figure 3). The data output state is concluded once 32-bits
the operating range (4.5V to 5.5V) before the end of the
are read out of the ADC or when CS is brought HIGH. The
POR time interval.
device automatically initiates a new conversion and the
cycle repeats.
Reference Voltage Range
Through timing control of the CS, SCK and EXT pins,
This converter accepts a truly differential external reference
the LTC2440 offers several fl exible modes of operation
voltage. The absolute/common mode voltage specifi cation
(internal or external SCK). These various modes do not for the REF+ and REF– pins covers the entire range from
require programming confi guration registers; moreover, GND to V . For correct converter operation, the REF+ pin
CC
they do not disturb the cyclic operation described above. must always be more positive than the REF– pin.
These modes of operation are described in detail in the
The LTC2440 can accept a differential reference voltage
Serial Interface Timing Modes section.
from 0.1V to V . The converter output noise is determined
CC
by the thermal noise of the front-end circuits, and as such,
Ease of Use
its value in microvolts is nearly constant with reference
The LTC2440 data output has no latency, fi lter settling
voltage. A decrease in reference voltage will not signifi -
delay or redundant data associated with the conversion
cantly improve the converter’s effective resolution. On the
cycle. There is a one-to-one correspondence between the
other hand, a reduced reference voltage will improve the
conversion and the output data. Therefore, multiplexing
converter’s overall INL performance.
multiple analog voltages is easy. Speed/resolution adjust-
ments may be made seamlessly between two conversions Input Voltage Range
without settling errors.
The analog input is truly differential with an absolute/com-
The LTC2440 performs offset and full-scale calibrations mon mode range for the IN+ and IN– input pins extending
every conversion cycle. This calibration is transparent to from GND – 0.3V to V + 0.3V. Outside these limits, the
CC
the user and has no effect on the cyclic operation described ESD protection devices begin to turn on and the errors
above. The advantage of continuous calibration is extreme due to input leakage current increase rapidly. Within these
stability of offset and full-scale readings with respect to limits, the LTC2440 converts the bipolar differential input
time, supply voltage change and temperature drift. signal, V = IN+ – IN–, from –FS = –0.5 • V to +FS =
IN REF
2440fd
10