Low-Power Variation-Tolerant Design in Nanometer Silicon [electronic resource]

2011·8.6 MB·English

by  Bhunia, Swarup

Low-Power Variation-Tolerant Design
in Nanometer Silicon

Swarup Bhunia Saibal Mukhopadhyay
·
Editors
Low-Power
Variation-Tolerant Design
in Nanometer Silicon
123
Editors
SwarupBhunia SaibalMukhopadhyay
DepartmentofElectricalEngineering SchoolofElectricaland
andComputerScience ComputerEngineering
CaseWesternReserveUniversity GeorgiaInstituteofTechnology
Cleveland,OH44106-7071,USA Atlanta,GA30332-0250,USA
[email protected] [email protected]
ISBN978-1-4419-7417-4 e-ISBN978-1-4419-7418-1
DOI10.1007/978-1-4419-7418-1
SpringerNewYorkDordrechtHeidelbergLondon
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Preface
Theenergyrequiredforrunningintegratedcircuits(ICs)isincreasingineverynew
generationofelectronicsystems.Atthesametimethemanufacturingprocessused
tobuildtheseICsarebecominglessdeterministic.Hence,low-powerdesignunder
largeparametervariationshasemergedasanimportantchallengeinthenanometer
regime.Thebook,forthefirsttime,integratesdescriptionoflowpowerandvaria-
tionissuesandprovidesdesignsolutionstosimultaneouslyachievelowpowerand
robustoperationundervariations.
Design considerations for low power and robustness with respect to variations
typically impose contradictory requirements. Power reduction techniques such as
voltage scaling, dual-threshold assignment and gate sizing can have large nega-
tiveimpactonparametricyieldunderprocessvariations.Thisbookintroducesthe
specific challenges associated with low power and variation-tolerant design in the
nanometertechnologyregimeatdifferentlevelsofdesignabstraction.Itconsiders
both logic and memory design aspects and encompass modeling, analysis as well
as design methodology to simultaneously achieve low power and variation toler-
ance while minimizing design overhead. The issue of device degradation due to
agingeffectsaswellastemporalvariationindeviceparametersduetoenvironmen-
tal fluctuations are also addressed. Micro-architecture level design modifications,
subthresholddesignissues,statisticaldesignapproaches,designoflow-powerand
robustdigitalsignalprocessing(DSP)hardware,analogandmixed-signalcircuits,
reconfigurablecomputingplatformssuchasfieldprogrammablegatearray(FPGA)
are covered. The book also discusses emerging challenges at future technology
nodes as well as methods industrial and academic researchers and engineers are
developingtodesignlow-powerICsunderincreasingparametervariations.
WhyaNewBook
Designing low power but reliable ICs using inherently unreliable process is a key
challenge in current generation ICdesign. The problem isescalating in every new
generation of ICs. The students, industrial/academic researchers, and practicing
engineers need to have basic understanding of this problem and knowledge of
v
vi Preface
existingandemergingmethodstoenabledesigningICsusingnanoscaleprocesses.
Currently,thereexistsnobookthatspecificallyaddressesthisproblem.Considering
the importance of the topic, the book compiles outstanding contributions from
prominent personalities in this area covering different aspects of low power and
variation-tolerantdesign.
UniqueFeatures
Introduction to the most important challenges in the area of low power and
•
variation-tolerantICdesigninnanoscaletechnologies.
Aholisticviewofthesolutionapproachesatdifferentlevelsofdesignabstraction
•
coveringdevice,circuit,architecture,andsystem.
Comprehensivecoverageonbothlogicandmemorycircuits.
•
Comprehensive coverage of system-level design – micro-architecture, DSP,
•
mixed-signal,andFPGA.
Modeling and analysis of different variation effects (die-to-die and within-die,
•
processandtemporal)onlowpowerdesigns.
Descriptionofultralowpowerandrobustsubthresholddesignaspects.
•
Description of technology scaling trends, emerging challenges, and future
•
researchdirections.
Organization andOverviewoftheContent
Thisbookisorganizedinfourintegratedparts,eachcoveringamajoraspectoflow
power and variation tolerance. The content of each part as well as each chapter in
thepartisdesignedtoprovidenecessarybackgroundtothereadersnewinthefield
as well as detailed discussions on state-of-the-art techniques for the experts in the
topic.PartIisdedicatedtoprovidethereaderacomprehensivebackgroundofthe
two complementary problems – power dissipation and parameter variations. The
backgrounds are supplemented with description of existing techniques for power
estimationandoptimizationaswellasvariationmodelingandcharacterization.The
rest of the book aims at establishing the principle that the challenge of low power
underprocessvariationsneedstobeaddressedatalllevelsofdesignabstraction,i.e.,
fromcircuitstologictomicro-architecturetosystem.PartIIfocusesoncircuitand
logicleveltechniquesincludingcomputer-aideddesignmethods;PartIIIdiscusses
system-levelmethodsforlowpowerunderprocessvariationsformicroprocessors,
digitalsignalprocessors,andanalog/RF/mixed-signalsystems.PartIVdiscussesthe
powerandvariationchallengesforreconfigurablecomputingplatformsandunique
design methods to address them, particularly focusing on Field-Programmable-
Gate-Arrays (FPGA). We will now provide a brief overview of each part of this
bookandthecorrespondingchapters.
Preface vii
PartI:PhysicsofPowerDissipationsandParameterVariations
PartIprovidesacomprehensivebackgroundofthetwocomplementaryproblems–
powerdissipationandvariations.Thispartisorganizedintwochapters–oneded-
icatedtobasicsofpowerdissipationandseconddedicatedtothebasicsofprocess
variations.Chapter1discussesthedifferentsourcesofvariationinCMOStechnolo-
giesandpresentsanoverviewofhowtocharacterizethesevariations.Thechapter
coversvarioussourcesofprocessvariationduringmanufacturing;sourcesofenvi-
ronmental variations including temperature and voltage fluctuations; and finally,
sources of temporal variations. Different state-of-the-art characterization circuits
and sensors employed in modern integrated circuits to understand the extent and
impact of variations are presented. An overview of the power dissipation issues
of the state-of-the-art CMOS technologies is presented in Chapter 2. This chapter
investigatesthesourcesofICpowerdissipationandtechniquesforpoweranalysis
innanometerCMOScircuits.Finally,differentpoweroptimizationtechniquesfrom
circuitandphysicaldesigntosystemsynthesisarediscussed.
PartII:Circuit-LevelDesignSolutions
Part II discusses the circuit-level challenges and design methodologies for low-
power and process variation tolerance. This part is organized in four chapters –
logiccircuits,statisticaldesign,memorycircuits,andultra-low-voltagedesign.
The process and temporal variations prevent a logic block from meeting tim-
ing and power criteria. The net effect is degradation in the parametric yield. The
low-power design methods like voltage scaling, dual threshold assignment further
magnify the effect of variations. A trivial solution to the problem of variation is
over-designing the logic circuit, for example, using transistor upsizing or supply
voltage boosting. But over-design comes at a serious power cost. Researchers at
industryandacademiahavebeenexploringmethodsthatwouldallowvariationtol-
eranceatnoorminimumpoweroverhead.Consideringthecomplexityofthecurrent
day integrated circuits, these methods span the domains of circuit design as well
as computer-aided design (CAD) methodologies. Chapter 3 reviews circuit-level
methods to address this goal. The chapter first analyzes the effect of process vari-
ations and time-dependent degradation mechanisms. The analysis is followed by
discussion of two design approaches to address these problems: variation tolerant
circuitsandadaptivecircuitsthattunethemselvestooperatecorrectlyundervaria-
tions.Chapter4ofthispartfocusesonthestatisticaldesignparadigm,asopposed
tothetraditionalcorner-basedmethodology,toaddressthevariationproblem.The
techniques for pre-silicon statistical timing and power analysis are presented to
determinetheperformancespreadoflargelogicblocksduetovariations.Next,the
pre-siliconstatisticaloptimizationtechniquesarediscussedtoimprovetheparamet-
ricyield.Finally,thechapterdiscusseshowasetofcompactsensorsmaybeused
topredictthedelayofamanufacturedpartanddriveadaptivepost-silicontuning.
viii Preface
The die-to-die or within-die spatial variations in process parameters are the
primary cause of concerns in logic circuits which lead to delay or leakage varia-
tions.Ontheotherhand,thememorycircuitsaremoresusceptibletolocalrandom
variationsthatresultsindifferenttypesofparametricfailures.Chapter5discusses
the impact of process variations on reliability of Static Random Access Memory
(SRAM).ThechapterprovidesanoverviewofthemechanismsofSRAMparamet-
ricfailuresandestimationmethodsforfailureprobabilitiesandparametricyieldof
SRAM.Thisanalysisisfollowedbydesignapproaches forSRAMyieldenhance-
ment including cell sizing, redundancy, dynamic circuit techniques, post-silicon
adaptiverepairtechniques,andvariation-tolerantSRAMperipherals.Finally,adis-
cussiononadaptivelowpowerandvariation-tolerantSRAMdesignformultimedia
applicationsisprovided.
This part concludes with the discussion of a relatively new concept of digi-
tal design – the subthreshold design – where operating voltage of the circuit is
lowerthanthethresholdvoltageofthetransistor.Theapplicationsofthesubthresh-
old design in ultra-low-power electronics are being actively investigated. Chapter
6 provides a brief overview of the principles and challenges subthreshold digital
design. Design principles at all levels of hierarchy, namely, devices, circuits, and
architecture, need to be evaluated for maximum power gains. Brief description of
SRAM design techniques as well as alternative architectures for lower power in
subthresholddesignhasalsobeendiscussed.
PartIII:System-LevelDesignSolutions
Part III focuses on system-level design challenges and design methodologies for
low-power and process-variation tolerance. The three chapters cover three differ-
ent types of mainstream electronic systems: microprocessor, application specific
integrated circuits such as digital signal processors, and analog/mixed Signal/RF
circuits.
Chapter 7 discusses micro-architectural techniques to tolerate variations in
microprocessorsanddesignvariation-tolerantlow-powersystems.Thechapterdis-
cusses how different variation sources impact the timing uncertainty atthe system
level. Designers typically account for parameter variations by inserting conserva-
tive margins that guard against worst-case variation characteristics to guarantee
functionalcorrectnessofthesystemunderalloperatingconditions.Butsuchconser-
vativeapproachesleadtoperformancedegradation.Thischapterpresentsalternative
error-tolerant schemes to deal with these different sources of parameter varia-
tions. Error-tolerant schemes aim to run with nominal timing-margins but without
comprisingrobustnessandcorrectness.
Chapter 8 presents an overview of low power and variation tolerant challenges
in digital signal processing (DSP) systems. The chapter discusses how to exploit
propertiesofDSPalgorithmsandcombinecircuitandarchitecture-leveltechniques
inordertoprovideintelligenttrade-offsbetweencircuit-levelmetricssuchaspower
Preface ix
andperformancewithsystem-levelmetricssuchasquality-of-resultsandtolerance
tovariations(yield).Thetechniquespresentedinthischaptertargetvarioustypesof
designsthatincludelogicandmemoryarchitecturesandcompleteDSPsystems.
Chapter 9 discusses challenges in analog/mixed Signal/RF systems and com-
plements the methodologies throughout the book for digital circuits and systems.
Low-Powerandvariation-tolerantanalog/mixedSignal/RFcircuitsrequireverydif-
ferentsetofdesigntechniques.Thedesigntechniquesrangefromindividualcircuit
components to system-level methods. This chapter highlights the component level
as well as system-level design challenges in a low-power, process-tolerant mixed
Signal/RF system using a wireless transceiver as a demonstration vehicle. At the
component level, variation-tolerance for critical blocks such as analog-to-digital
conversion, low-noise amplifiers are discussed. At the system level, the chapter
focuses on how to achieve low power and end-to-end quality-of-service in RF
transceiverunderbothmanufacturingandenvironmentalvariations.
PartIV:Low-PowerandRobustReconfigurableComputing
Part IV concentrates on low power and variation tolerance in reconfigurable
computing platforms. FPGAs are reconfigurable devices that can be programmed
after fabrication to implement any digital logic. Compared to application-specific
integratedcircuitsorASIC,FPGAprovidesflexibility,in-fieldreconfigurability,and
potentialcostadvantagebutattheexpenseofarea,performance,andperhapsmost
importantlypower.FPGAsarenormallylesspowerefficientthanASICsbutsignifi-
cantresearcheffortsdevotedtoimprovingpowerefficiencyofFPGAcanpotentially
narrow or even close this gap. Chapter 10 surveys the techniques and progress
madetoimproveFPGApowerefficiency.Parametervariationandcomponentaging
arebecomingasignificantproblemforalldigitalcircuitsincludingFPGAs.These
effectsdegradeperformance,increasepowerdissipation,andcausepermanentfaults
atmanufacturingtimeandduringthelifetimeofanFPGA.Chapter11examinesthe
impactofvariationanddevicewear-outonFPGAs.Thechapterdiscussesdifferent
techniques that can be used to tolerate variations in FPGA with specific attention
to how the reconfigurable nature of the FPGAs can lead to innovative solutions to
variationandwear-outmanagement.Chapter12discussesdesignmethodsthatcan
providebothlowpowerandvariationtolerance.Thischapterdiscussestheopportu-
nitiesofusingpost-fabricationreconfigurationinFPGAtotoleratevariationeffects
withoutexpensivestaticmargins.Thepost-fabricationreconfigurabilitycanbeused
todeploydevicesbasedontheirfabricatedoragedcharacteristicstoplacethehigh-
speed/leaky devices on critical paths and slower/less-leaky devices on non-critical
paths.Thecomponent-specificmappingmethodologiesthatcanachievetheabove
objectivesarediscussedinthechapter.
We believe the target readership consisting of students, researchers, and prac-
titioners will like the content and be greatly benefited from it. We also believe