Low Power Current Mode Delta-Sigma ADC using Ring Oscillator based Quantizer

78 Pages·2013·1.79 MB·English

Low Power Current Mode Delta-Sigma
ADC using Ring Oscillator based
Quantizer
IBRAHIM KAZI
Degree project in
System on Chip Design
Second cycle
Stockholm, Sweden 2013
TRITA-ICT-EX-2013:11
www.kth.se
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Low Power Current Mode ∆ ADC using a Ring
Oscillator based Quantizer.
Thesis by
Ibrahim Kazi
School of Information and Communication Technology
Royal Institute of Technology, Sweden
In Partial Fulfillment of the Requirements
For the Degree of
Master of Science in System on Chip Design
Supervisor Nikola Katic, LSM, EPFL
Prof.Alexandre Schmid, LSM, EPFL
Stockholm, Sweden
January, 2013
ACKNOWLEDGEMENTS
I would like to thank Dr.Alexandre Schmid and Nikola Katic for providing me the
opportunity for this thesis at the Microelectronics Systems Lab, EPFL. Nikola helped
me a lot in the design phase and simulations during this thesis, for this I am greatly
indebted to him. I would like to thank Prof.Dr.Ana Rusu from school of ICT KTH,
for not only agreeing to be my thesis examiner, but also equipping me with the
necessary knowledge about data converters to undertake a masters thesis in this field.
Particulary her advanced mixed mode design course which helped me a long way
in this thesis. I would like to thank Dr.Saul Rodriguez Duenas for teaching us the
qualitative way of analyzing analog circuits. The atmosphere here at LSM lab has
been very conducive towards research, for this I thank the LSM group members. I
am forever thankful to my family who have supported me in every way possible and
for being there for me.
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ABSTRACT
Low power ADCs have wide range of applications, from battery operated systems like
biomedical devices to on chip power measurement systems. A more digital implemen-
tation is also desirable to take advantage of the technology scaling in digital CMOS
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technologies. This thesis explores the idea of a low power continuous time ∆ ADC
using current mode signaling. It achieves a second order noise shaping by using a first
order current filter, a digital difference block and a current controlled ring oscillator.
This type of ADC has a mostly digital implementation, as the main analog blocks
are the current-mode filter and two op-amps which are used for biasing.
The behavioral level ADC is implemented in VerilogA and the transistor level ADC
is deisgned in CADENCE using UMC 180nm process. MonteCarlo simulations are
also performed to ensure the proper operation of the current-mode filter in presence
of mismatches, as log-domain filters are very sensitive to transistors mismatches.
The ADC performance obtained from transistor level simulation is 7.3 Effective Num-
ber of Bits (ENOB) over 30KHz bandwidth and 5.3µW power consumption.
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TABLE OF CONTENTS
List of Figures 7
List of Abbrevations 10
1 Introduction 12
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Author Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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2 ∆ ADC using Oscillator Based Quantizer 15
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2.1 Background on ∆ Modulation . . . . . . . . . . . . . . . . . . . . 15
2.2 State of the art ADCs with Oscillator Based Quantizer . . . . . . . . 18
2.3 Oscillator Based Quantizer . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 First Order Noise Shaping . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Ring Oscillator Quantizer and Edge Detection Circuit . . . . . 21
2.3.3 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . 22
2.3.4 Closed-Loop Operation . . . . . . . . . . . . . . . . . . . . . . 23
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3 Proposed Current Mode ∆ ADC with a Ring Oscillator Based
Quantizer 25
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3.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Behavioral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 Ring Oscillator Quantizer . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 Inverter Cell for Ring Oscillator Quantizer . . . . . . . . . . . 30
3.3.2 Sustained Oscillations . . . . . . . . . . . . . . . . . . . . . . 33
3.3.3 Inverter Cell with Replica Bias and Input Current Mirror . . . 36
3.3.4 13 stage Ring Oscillator . . . . . . . . . . . . . . . . . . . . . 37
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3.3.5 Simulation of ∆ ADC using Ring Oscillator implemented at
transistor level . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 Current-Mode Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.1 Current Conveyor based Current Integrator-I . . . . . . . . . . 39
3.4.2 Current Integrator-II . . . . . . . . . . . . . . . . . . . . . . . 42
3.4.3 Companding Current Integrator-III . . . . . . . . . . . . . . . 43
3.4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . 48
3.5.1 Data Weighted Averaging . . . . . . . . . . . . . . . . . . . . 49
3.5.2 Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5.3 Simulation Results using Transistor Model for DAC and Digital
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.6 OTAs for Replica Bias and Gain Boosted Current Mirror . . . . . . . 54
4 Simulation Results - Behavioral Level and Transistor Level 56
4.1 SNR and SNDR Results . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 MonteCarlo Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 Overall ADC Performance . . . . . . . . . . . . . . . . . . . . . . . . 63
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4.4 Comparison with other state of the art CT-∆ ADC . . . . . . . . 64
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5 Conclusions and Future Work 66
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Appendices 68
A Appendix A Verilog-A Code for Oscillator Model 69
References 71
List of Figures
2.1 Spectrum of quantization noise at two different sampling frequencies.
The shaded area shows the inband quantization noise . . . . . . . . . 16
2.2 Spectrum of quantization noise with noise shaping. The shaded area
shows the inband quantization noise . . . . . . . . . . . . . . . . . . 17
2.3 ADC in a feedback loop . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Linear model of an ADC in a feedback loop . . . . . . . . . . . . . . 18
2.5 First order noise shaping in oscillator based Analog to Digital Con-
verter (ADC).[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 Frequency to digital converter . . . . . . . . . . . . . . . . . . . . . . 21
2.7 Ring Oscillator with First Order Difference Logic [1] . . . . . . . . . 22
2.8 Open loop model of a Ring Oscillator Quantizer (ROQ) . . . . . . . . 24
2.9 Model of ROQ in a feedback loop . . . . . . . . . . . . . . . . . . . . 24
3.1 Complete Block Level Diagram . . . . . . . . . . . . . . . . . . . . . 26
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3.2 Power Spectral Density of the VerilogA model of the ∆ ADC.Input:
-12dBFS, 2.75KHz, Bandwidth: 25KHz, Sampling frequency: 1.024MHz 29
3.3 SNR and SNDR vs Input amplitude . . . . . . . . . . . . . . . . . . . 29
3.4 SNR and SNDR vs Input amplitude for a non-linear frequency tuning
curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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3.5 Inverter Cell for the Ring Oscillator . . . . . . . . . . . . . . . . . . . 31
3.6 Even inverter ring with differential inverters . . . . . . . . . . . . . . 31
3.7 PMOS bulk-drain connected load for inverter cell . . . . . . . . . . . 32
3.8 Magnitude and Phase response of a single inverter cell of the ring
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.9 (a)ReplicaBiasforconstantoutputswing. (b)Inverterwithhighimpedance
current mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10 Current Controlled Ring Oscillator Linearity and Curve Fitting Show-
ing Third Order Polynomial . . . . . . . . . . . . . . . . . . . . . . . 37
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3.11 Power Spectral Density of ∆ ADC with transistor based Oscillator
and parasitic load capactance.Input: -12dBFS, 2.75KHz, Bandwidth:
25KHz, Sampling frequency: 1.024MHz . . . . . . . . . . . . . . . . . 38
3.12 Current Conveyor symbol . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Current Conveyor schematic . . . . . . . . . . . . . . . . . . . . . . . 41
3.14 Current Conveyor based current integrator . . . . . . . . . . . . . . . 41
3.15 Second Integrator: Mismatches between M1 and M4 cause a large bias
current variation if the transistors are in subthreshold . . . . . . . . . 42
3.16 An example of a translinear loop . . . . . . . . . . . . . . . . . . . . 44
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3.17 Companding Integrator used in the ∆ ADC . . . . . . . . . . . . . 45
3.18 Differential to single ended conversion . . . . . . . . . . . . . . . . . . 47
3.19 SNDR and SNR vs Input Amplitude . . . . . . . . . . . . . . . . . . 47
3.20 Schematic of the feedback DAC . . . . . . . . . . . . . . . . . . . . . 48
3.21 CircuittocreateaNegativeReplicaoftheDACOutputCurrent. (W =
L
0.24µm for all transistors) . . . . . . . . . . . . . . . . . . . . . . . . . 49
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3.22 Each element of the DAC is accessed almost equally over one period
of the test signal. (Test signal -12dBFS, 2.75KHz) . . . . . . . . . . . 50