Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP

31 Pages·2000·0.34 MB·English

by  Texas Instruments, Incorporated

Application Report
SLAA111 - November 2000
Interfacing the TLV2541 ADC and the TLV5618A DAC to
the TMS320C31 DSP
Joselito Parguian AAP Data Converters
ABSTRACT
This application report is written to help design engineers or technicians implement a simple
data acquisition system using serial analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs) from Texas Instruments. A hardware and software
solution for interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP
with the use of the TMS320C3x DSP starter kit (DSK) is presented here.
In addition, the new multi-converter EVM (EVM0309) from Texas Instruments is briefly
discussed, since this is the evaluation module used to demonstrate the functionality of both
ADCs and DACs.
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Host PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 TMS320C3x DSP Starter Kit (DSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 DSK Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 The Multi-Converter EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 The TMS320C31 DSP Bidirectional Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Serial-Port Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 FSX/DX/CLKX Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 FSR/DR/CLKR Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Receive/Transmit Timer-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Receive/Transmit Timer-Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Receive/Transmit Timer-Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 Serial-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 Serial-Port Initialization/Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.9 Serial Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 The ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 TLV2541 Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 The DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 The DAC Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 The DAC Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 DAC Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 The System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1
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6.1 Operation and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Appendix A TLV2541.ASM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix B Program and Data Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of Figures
1 Serial-Port Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Serial-Port Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 FSX/DX/CLKX Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FSR/DR/CLKR Port-Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Receive/Transmit Timer-Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Receive/Transmit Timer-Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Receive/Transmit Timer-Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8 TLV2541 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 Typical Hardware Configuration for a Glueless Logic Connection (Dedicated Device) . . . . . . . . . . . 16
10 Alternative Hardware Configuration for a Glueless Logic Connection (Dedicated Device) . . . . . . . 17
11 Timing Diagram (CS = 0, FS = Frame Sync Signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12 Timing Diagram (CS = Frame Sync Signal, FS = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Hardware Configuration for Devices Sharing the DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14 Timing Diagram (CS = Chip Select, FS = Frame Sync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
15 Functional Block Diagram of the TLV5618A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16 DSP Data Manipulation of ADC Data for DAC Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17 DAC Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18 DAC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19 Hardware Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
20 ADC and DAC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
21 Illustration of the Complete Data Acquisition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of Tables
1 List of Serial Analog-to-Digital Converters Supported by the Multi-Converter EVM . . . . . . . . . . . . . . . 6
2 List of Serial Digital-to-Analog Converters Supported by the Multi-Converter EVM . . . . . . . . . . . . . . . 6
3 Registers Associated With the Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Serial-Port Global Control Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Receive/Transmit Timer-Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6 Register-Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP
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1 Introduction
Texas Instruments provides a wide variety of digital signal processors (DSPs). While there are
many TI DSPs to choose from, this application report will focus on the TMS320C31 DSP for
simplicity. The TMS320C31 DSP is a high-performance CMOS 32-bit floating-point digital signal
processor. The ’C31 DSP integrates both system control and math-intensive functions on a
single controller and is capable of 25 million instructions per second (MIPS) and 50 million
floating-point operations per second (MFLOPS). This processor provides a total memory space
of 16 million 32-bit words that contain program, data, and I/O space. Two RAM blocks of 1K × 32
bits each and a boot loader permits the ’C31 DSP to perform two CPU accesses in a single
cycle. A 64 × 32-bit instruction cache is also provided to store often-repeated sections of code to
reduce the number of off-chip accesses. The ’C31 DSP has one standard, bidirectional serial
port, which will be the main focus of this report for interfacing the ADC and the DAC. The
TMS320C3x DSK is used to facilitate interfacing the ADC and DAC to the DSP.
The TLV2541 is a high-performance, 12-bit, low-power, CMOS analog-to-digital converter
(ADC). The architecture of this device is based upon a successive approximation register (SAR).
This ADC operates from a single wide-range power supply, typically from a minimum of 2.7 V to
a maximum of 5.5 V. This device is designed to operate with very low power consumption, with
power savings further enhanced by an auto-power-down mode. The conversion speed is not
programmable, because the device uses only a built-in oscillator as its source of conversion
clocking. The built-in oscillator provides a fixed conversion time of 3.5 m s.
The TLV5618A is a dual 12-bit voltage output DAC and is also a CMOS device. This device is
designed to operate from a single, wide-range supply voltage. The dual channel output of the
DAC is buffered by a 2×-gain rail-to-rail output buffer. The buffer features a Class-AB output
stage to improve stability and reduce settling time. The programmable settling time allows the
designer to optimize speed versus power dissipation. The DAC is specifically included to
reconstruct the original analog input of the ADC for verification purposes. The DAC output is an
approximation of the ADC input signal.
This application report therefore provides an overview of the hardware interface as well as the
software interface. It should aid the user to become familiar with the DSP as well as the data
converters used. The software programs included in this report will also allow the user to be
quickly acquainted with the data converters and the DSP standard serial port.
2 Hardware
The hardware consists of a host PC, the TMS320C3x DSK, and the multi-converter evaluation
module.
2.1 Host PC
The following is a list of the minimum recommended requirements for the host PC:
• An IBM PC/ATor 100%-compatible PC
•
Hard disk drive
•
Floppy-disk drive
IBM and AT are trademarks of International Business Machines Corporation.
Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP 3
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•
640 Kbytes minimum memory
•
Monochrome or color display (color recommended)
•
Parallel printer port communication link
•
Straight-through parallel printer port cable
• MS-DOS or PC-DOS (version 5.0 or later), Windows or OS/2 operating system
•
XDS510 emulator card (optional)
•
MPSD cable (optional)
The optional XDS510 (TI P/N TMDS00510M, MPSD cable and emulator card) emulator is
preferred if available.
The assembly program provided in this report, to interface the data converters to the DSP, is
written using Code Composer software. If the DSK assembler/debugger is preferred over
Code Composer software, then the program provided in the appendix section of this report
must be modified slightly to suit the DSK assembler environment. You can use almost any ASCII
program editor to create and modify a DSK assembler source file. The modification consists of
adding an assembler directive to the beginning of the program to tell the assembler where to
start the program. You must ensure that the assembler directive (opcode) is not in the first
column, otherwise it is interpreted as a label. An example of proper opcode positioning is shown
in bold in the following code sequence.
.start “SP0TEST”, 0x809802
.sect “SP0TEST”
;=========================================================================
; Serial Port 0 registers
;=========================================================================
sport .set 808040h ; Serial Port 0 global control register
xpctrl .set 808042h ; FSX/DX/CLKX port control
.
.
.
Refer to the TMS320C3x DSP Starter Kit User’s Guide (literature number SPRU163) for more
details in creating the assembler source codes.
2.2 TMS320C3x DSP Starter Kit (DSK)
Texas Instruments provides this TMS320C3x DSK, a low-cost, easy-to-use, high-performance,
and expandable development platform that lets you experiment and develop real-time signal
processing applications with the TMS320C3x DSP. This particular DSK has a TMS320C31 DSP
onboard to allow full-speed verification of the TMS320C3x code. The DSK also gives you the
freedom to develop your own software on a PC and run it on the DSK board. The DSK can
interface to a host PC through the parallel printer port or through the use of the modular port
scan device (MPSD) port interface to control the on-chip emulation. The MPSD interface
requires additional accessories such as the MPSD cable and an emulator card as discussed in
section 2.1.
MS-DOS and Windows are trademarks of Microsoft Corporation.
OS/2 is a trademark of International Business Machines Corporation.
Other trademarks are the property of their respective owners.
4 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP
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TMS320C31 DSK features are:
•
Industry-standard TMS320C31 floating-point DSP
•
40-ns instruction cycle time, 50 MFLOPS, 25 MIPS
• Standard or enhanced parallel printer port interface which connects to a host PC allows the
TMS320C31 DSP to communicate with PC programs
•
Analog data acquisitions via the TLC32040 analog interface circuit (AIC):
– Variable rate analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with
14-bit dynamic range at 20 kSPS
– Output reconstruction filter and bypassable, switched-capacitor antialias input filter
•
Standard RCA plug connectors for analog input and output that provide a direct connection
to microphone and speaker
•
XDS510 emulator connector (Note: jumper and header are not installed)
•
Expansion connectors, which route all the TMS320C31 pins for use with DSK
daughterboards
2.2.1 DSK Overview
The DSK hardware is a complete platform solution for the development of any conceivable
project that requires the processing power of the TMS320C31 DSP. This DSK can be used to
interface and communicate directly to a host PC and allow you to create your own software,
download the software onto the DSK, and run the software on the DSK board. It also gives you
the freedom to evaluate the onboard analog interface circuit (AIC) or analyze external analog
input and output signals through the two RCA connectors provided onboard. The TLC32040 AIC
interfaces to the TMS320C31 DSP serial port. A jumper block allows removal of this connection
to route the serial port to a user-supplied DSK daughterboard.
Refer to the TMS320C3x DSP Starter Kit User’s Guide (literature number SPRU163) for more
information regarding DSK installation and operation.
2.3 The Multi-Converter EVM
Texas Instruments offers a low-cost solution for customers who would like to quickly evaluate
certain devices through the use of an evaluation module (EVM). The EVM used for this report is
the multi-converter EVM (P/N MULTICNVTR-EVM), a platform designed to evaluate families of
8-pin serial ADCs and DACs under various signal, reference, and supply conditions. Although
the multi-converter EVM is used in this report, coverage includes only the ADC and DAC
devices mentioned previously. This does not prevent the use of any other devices listed in
Table 1 and Table 2, provided that the user is familiar with devices not discussed in this report.
Alternatively, the user can refer to the device data sheet and the Multi-Converter EVM User’s
Guide (literature number SLAU047A) for information. Parts in bold letters are the only devices
discussed in this report.
Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP 5
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Table 1. List of Serial Analog-to-Digital Converters Supported by the Multi-Converter EVM
PART NUMBER INPUT CHANNELS INPUT SIGNAL MAXIMUM THROUGHPUT
TLV2541 Single Unipolar 200 kSPS
TLV2542 Dual with autosweep Unipolar 200 kSPS
TLV2545 Single with pseudo-differential Pseudo-differential 200 kSPS
TLC2551 Single Unipolar 400 kSPS
TLC2552 Dual with autosweep Unipolar 400 kSPS
TLC2555 Single with pseudo-differential Pseudo-differential 400 kSPS
Table 2. List of Serial Digital-to-Analog Converters Supported by the Multi-Converter EVM
PART NUMBER RESOLUTION (BITS) OUTPUT CHANNEL INTERNAL REFERENCE
TLV5623 8 1 No
TLV5624 8 1 Yes
TLV5625 8 2 No
TLV5626 8 2 Yes
TLV5606 10 1 No
TLV5617A 10 2 No
TLV5637 10 2 Yes
TLV5616 12 1 No
TLV5618A 12 2 No
TLV5636 12 1 Yes
TLV5638 12 2 Yes
The multi-converter EVM is also capable of operating continuously in stand-alone mode (SAM).
This feature is very useful when checking the functionality of the EVM itself, or the ADC or DAC
device when a host DSP is not readily available. A quick reference guide (QRG) is included in
the package when ordering this multi-converter EVM. The QRG will assist the user to configure
the EVM quickly for the different data converter combination setups, and to have it up and
running in a minimum amount of time.
3 The TMS320C31 DSP Bidirectional Serial Port
The TMS320C31 DSP has one standard bidirectional serial port. The TMS320C31 serial port is
a versatile communication channel that allows interfacing to most serial interface analog
conversion chips without glue logic. The serial port can be configured to transfer 8, 16, 24, or 32
bits of data per word simultaneously in both directions. The clock for the serial port can be
supplied externally, or can originate internally through the serial port timer and period registers.
The internally generated clock is a divide-down of the clock-out (CLKOUT) frequency, f . This
(H1)
is discussed in Section 3.7.
The serial port is used to transmit and receive data between the DSP and the ADC, and the
configuration described below is specific to the way that the DSP communicates with the ADC
for this application. Note that the user can always tailor the configuration to situation
requirements. The DSP serial port requires a little more time and understanding when initializing
and configuring, compared to the data converters. Therefore, this report will explain the serial
interface in some detail. Six control lines from the DSP are used to interface to the data
converters:
6 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP
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CLKX Transmit frame synchronization input or output
This signal clocks data from the transmit shift register (XSR) to the data transmit
(DX) pin. The serial port can be configured for internal clock generation or to
accept an external clock. If the port is configured to generate the data clock
on-chip, CLKX becomes an output, providing the data clock for the serial interface.
If the port is configured to accept an external clock, CLKX changes to an input,
receiving the external clock signal.
FSX Transmit frame synchronization input or output
FSX indicates the start of a data transfer. The serial port can be configured for
internal frame-sync generation or to accept an external frame-sync signal. If the
port is configured to generate the frame-sync pulse on-chip, FSX becomes an
output. If the port is configured to accept an external frame-sync pulse, this pin
becomes an input.
DX Serial data transmit
DX transmits the actual data from the transmit shift register (XSR).
CLKR Receive clock input
CLKR always receives an external clock for clocking the data from the data
receive (DR) pin into the receive shift register (RSR).
FSR Receive frame synchronization input
FSR always receives an external frame-sync pulse to initiate the reception of data
at the beginning of a frame.
DR Serial data receive
DR receives the actual data which are clocked into the receive shift register
(RSR).
In addition to these six control lines, there are control, shift, and buffer registers that are all 32
bits wide. These 32-bit wide registers support the standard serial port interface operation of the
DSP. Each of these registers, except for the two shift registers (XSR and RSR), is located in its
specific address mapped in memory. Table 3 shows the register names and their respective
addresses, and the values used for configuration.
Table 3. Registers Associated With the Serial Port
REGISTER NAME ADDRESS (Hex) VALUE (Hex)
Serial-port global control 808040 0C140044
FSX / DX / CLKX port-control 808042 00000111
FSR / DR / CLKR port-control 808043 00000111
R / X timer-control 808044 000001CF
R / X timer-counter 808045 00000000
R / X timer-period 808046 00000000
Data-transmit (DXR) 808048 Variable
Data-receive (DRR) 80804C Variable
The control registers contain the control bits set by the CPU to configure the operation of the
standard serial port. The addressable buffer registers, DXR and DRR, are discussed further in
Serial Port Operation, Section 3.9.
Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP 7
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3.1 Serial-Port Global Control Register
The first thing to do is to define how the serial-port global control register (GCR) controls the
function of the serial port and determines its operating mode. The physical structure of the serial
port global control register is shown in Figure 1, and the function of the serial port global control
bits is described in Table 4. The serial port GCR is mapped in memory location 808040 hex and
is referred as the serial port base address.
SERIAL-PORT GLOBAL CONTROL REGISTER (Upper Word)
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NAME RRESET XRESET RINT RTINT XINT XTINT RLEN XLEN FSRP FSXP
TYPE X X X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0
SERIAL-PORT GLOBAL CONTROL REGISTER (Lower Word)
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAME DRP DXP CLKRP CLKXP RFSM XFSM RVAREN XVAREN RCLK XCLK HS RSR XSR FSXOUT XRDY RRDY
SRCE SRCE FULL EMPTY
TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R
DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
NOTE: R = read, W = write, X = reserved bit, read as 0
Figure 1. Serial-Port Global Control Register
8 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP
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Table 4. Serial-Port Global Control Register Definition
BIT NAME FUNCTION
0 RRDY RECEIVER READY (if 1, DRR has new data and is ready to be read; if 0, DRR has no new data)
1 XRDY TRANSMITTER READY (if 1, DXR has written the last bit of data to XSR and is ready for new data; if 0, DXR has
not written the last bit of data to XSR and is not ready for a new data)
2 FSXOUT TRANSMIT FRAME SYNC (if 1, FSX is configured as an input; if 0, FSX is configured as an output)
3 XSREMPTY TRANSMIT SHIFT REGISTER (if 1, XSR is not empty; if 0, XSR is empty; Reset and XRESET causes this bit to be
set to 0)
4 RSRFULL RECEIVE SHIFT REGISTER (if 1, RSR and DRR are full; if 0, no overrun of the receiver has occurred)
5 HS Handshake mode enable (if 1, HS is enabled; if 0, HS is disabled)
6 XCLK SRCE TRANSMIT CLOCK SOURCE (if 1, the internal transmit clock is used; if 0, the external transmit clock is used)
7 RCLK SRCE RECEIVE CLOCK SOURCE (if 1, the internal receive clock is used; if 0, the external receive clock is used)
8 XVAREN TRANSMIT DATA RATE MODE (if 1, data rate is variable and FSX is held active while all bits are being transmitted;
if 0, data rate is fixed and FSX is only active for at least one XCLK cycle)
9 RVAREN RECEIVE DATA RATE MODE (if 1, data rate is variable and FSR is held active while all bits are being received; if 0,
data rate is fixed and FSR is only active for at least one RCLK cycle)
10 XFSM TRANSMIT FRAME SYNC MODE (if 1, mode is continuous and FSX is only generated at the start of the first word
of a block transmitted; if 0, mode is standard and FSX is generated for every word transmit)
11 RFSM RECEIVE FRAME SYNC MODE (if 1, mode is continuous and FSR is only generated at the start of the first word of
a block received; if 0, mode is standard and FSR is generated for each word received)
12 CLKXP TRANSMIT CLOCK POLARITY (if 1, CLKX is active low; if 0, CLKX is active high)
13 CLKRP RECEIVE CLOCK POLARITY (if 1, CLKR is active low; if 0, CLKR is active high)
14 DXP DATA TRANSMIT POLARITY (if 1, DX is active low; if 0, DX is active high)
15 DRP DATA RECEIVE POLARITY (if 1, DR is active low; if 0, DR is active high)
16 FSXP TRANSMIT FRAME SYNC POLARITY (if 1, FSX is active low; if 0, FSX is active high)
17 FSRP RECEIVE FRAME SYNC POLARITY (if 1, FSR is active low; if 0, FSR is active high)
18–19 XLEN TRANSMIT WORD LENGTH ( 8/16/24/32 )
20–21 RLEN RECEIVE WORD LENGTH ( 8/16/24/32 )
22 XTINT TRANSMIT TIMER INTERRUPT ENABLE (if 1, transmit timer interrupt is enabled; if 0, transmit timer interrupt is
disabled)
23 XINT TRANSMIT INTERRUPT ENABLE (if 1, transmit interrupt is enabled; if 0, transmit interrupt is disabled)
24 RTINT RECEIVE TIMER INTERRUPT ENABLE (if 1, receive timer interrupt is enabled; if 0, receive timer interrupt is
disabled)
25 RINT RECEIVE INTERRUPT ENABLE (if 1, receive interrupt is enabled; if 0, receive interrupt is disabled)
26 XRESET TRANSMIT RESET (if 1, the transmit side of the serial port is taken out of reset; if 0, transmit side of the serial port is
reset)
27 RRESET RECEIVE RESET (if 1, the receive side of the serial port is taken out of reset; if 0, receive side of the serial port is
reset)
28–31 RESERVE BITS READ AS ZERO
Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP 9
SLAA111
Figure 2 shows in both binary and hex format the code that is loaded into the serial-port global
control register.
BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VALUE (BIN) X X X X 1 1 0 0 0 0 0 1 0 1 0 0
VALUE (HEX) 0 C 1 4
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE (BIN) 0 0 0 0 0 0 0 0 0 1 0 R R 1 R R
VALUE (HEX) 0 0 4 4
NOTE: X represents reserved bits and R are read-only bits.
Figure 2. Serial-Port Configuration Word
The configuration word chosen for the serial-port GCR configures the serial port as follows:
•
FSX pin is configured as an output pin.
•
Handshake mode is disabled.
•
Internal transmit clock is used.
•
External receive clock is used.
•
Fixed data rate mode is chosen when transmitting and receiving.
•
Receive and transmit frame sync mode selected as standard mode, where each word
transmitted or received has an associated sync pulse.
•
CLKX and CLKR polarity are chosen as active high.
•
DX and DR polarity are chosen as active high; FSX and FSR polarity are chosen as active
high.
•
Transmit and receive word lengths are 16 bits.
•
Transmit and receive timers and interrupts are disabled.
•
Transmit and receive sides are set to take out of reset mode.
3.2 FSX/DX/CLKX Port-Control Register
This 32-bit port-control register controls the function of the serial port FSX, DX, and CLKX pins.
Each pin function is described by four bits as follows:
•
Bit 0, FUNC: Function. General-purpose I/O pin if 0; serial-port pin if 1
•
Bit 1, I/O: Input/output. General-purpose input pin if 0; general-purpose output pin if 1
•
Bit 2, DATOUT: Data output to pin if selected as general-purpose output pin
•
Bit 3, DATIN: Data input on pin if selected as general-purpose input pin
Therefore, bits [3:0] describe the use of the CLKX pin, bits [7:4] describe the use of the DX pin,
and bits [11:8] describe the use of the FSX pin. The rest of the bits (bits [31:12]) are reserved
and read as zero. See Figure 3.
10 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP