inmos :: transputer :: 72-TRN-228-00 The T9000 Transputer Products Overview Manual 1991

211 Pages·1991·13 MB·English

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THE T9000
TRANSPUTER
PRODUCTS
OVERVIEW
MANUAL
First Edition 1991
i...,I ~i~@m~'i~~JI
®
INMOS IS a member of the SGS-THOMSON Microelectronics Group
INMOS Databook series
Transputer Databook
Military and Space Transputer Databook
Transputer Development and iq Systems Databook
Graphics Databook
Transputer Applications Notebook: Architecture and Software
Transputer Applications Notebook: Systems and Performance
The T9000 Transputer Products Overview Manual
Copyright © INMOS Limited 1991
INMOS reserves the right to make changes in specifications at any time and without notice.
The information furnished by INMOS in this publication is believed to be accurate; however,
no responsibility is assumed for its use, nor for any infringement of patents or other rights of
third parties resulting from its use. No licence is granted under any patents, trademarks or oth
er rights of INMOS .
• , ~lJ'ilmOS~IMS and occam are trademarks of INMOS Limited.
iiii iiii@m~l~~©'i is a registered trademark of SGS-THOMSON Microelectronics Group.
INMOS is a member of the SGS-THOMSON Microelectronics Group.
INMOS document number: 72 TRN 228 00
ORDER CODE: DBTRANSPST/1
Contents overview
I
Contents....................................................... v
Preface .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xiii
Part 1: Product Family Overview ................................... 1
Introducing the INMOS IMS T9000 family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 The IMS T9000 transputer .............................................. 7
3 Simplicity of system design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Protection and error handling ........................................... 20
5 Support for multiprocessing. . . . . . . . .. .................................. 22
6 Communication links .................................................. 28
7 Network communications .............................................. 35
8 Other communications devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Software and systems ................................................. 45
10 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Part 2: Product Family Preliminary Information ....................... 53
IMS T9000 transputer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IMS C104 packet routing switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . .. 139
IMS C100 system protocol converter ........................................... 163
iv Contents overview
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. xiii
Part 1: Product Family Overview ................................... 1
1 Introducing the INMOS IMS T9000 family . . . . . . . . . . . . . . . . . . . . . . . 3
1. 1 Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Multiprocessing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Communications support devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. 4 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1. S Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S
2 The IMS T9000 transputer ................................... 7
2.1 Overview ........................................................... . 7
Processor .................................................. . 7
Hierarchical memory system .................................. . 8
Communications system ..................................... . 8
Multiple internal buses ....................................... . 8
System services ............................................ . 9
2.2 The transputer architecture ............................................ . 9
2.3 Support for concurrent processes ....................................... . 10
2.4 Pipelined, superscalar implementation ................................... . 10
The pipeline ................................................ . 11
Grouping of instructions ...................................... . 11
Improvements over IMS T80S .................................. . 12
2.S Hierarchical memory system ........................................... . 12
2.S.1 Main cache ................................................ . 13
Cache operation ............................................ . 13
Use as on-Chip RAM ......................................... . 14
2.S.2 Workspace cache ........................................... . 14
Cache operation ............................................ . 14
3 Simplicity of system design ................. . . . . . . . . . . . . . . . . . 16
3.1 Single SMHz clock input ............................................... 16
3.2 Programmable memory interface ........................................ 16
3.3 Control links and configuration .......................................... 16
3.4 Loading and bootstrapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 17
3.S Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . . . . .. . . . . .. . . . . . . . 18
4 Protection and error handling ................................ 20
4.1 Error handling ........................................................ 20
4.2 Protected mode ...................................................... 20
Protected mode processes .................................... 20
Executing illegal instructions ................................... 20
Memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
vi Contents
5 Support for multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22
Fast interrupt response and process switch . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 The transputer model of concurrency ..................................... 22
Processes and channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Example.................................................... 23
Multiprocessor programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Other models of concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Shared memory .............................................. 25
5.3 Hardware scheduler ................................................... 26
5.4 Interrupts, events and timers ............................................ 26
5.5 Shared resources ..................................................... Z7
6 Communication links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28
6.1 Using links between transputers ......................................... 28
6.2 Advantages of using links. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Efficiency ................................................... 28
Simplicity ................................................... 28
Hardware independence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 IMS T9000 links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 Virtual channels .............................................. 30
Virtual links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Sending packets ............................................. 31
Receiving packets ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
The virtual channel processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.2 Levels of link protocol. ........................................ 32
Packet level protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Token level protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Bit level protocol ............................................. 33
7 Network communications ................................. . .. 35
7.1 Message routing ..................................................... . 35
Advantages for the programmer ................................ . 35
Routers .................................................... . 35
Separating routers and processors .............................. . 36
Parallel networks ............................................ . 36
7.2 The IMS C104 ....................................................... . 36
Wormhole routing ............................................ . 36
Minimizing routing delays ..................................... . 37
Control links ................................................ . 38
7.2.1 Using IMS T9000s with IMS C104s .............................. . 38
Header deletion ............................................. . 38
Routing control channels ...................................... . 40
7.3 Routing algorithms ........................... : ....................... . 40
7.3.1 Labelling networks ........................................... . 41
7.3.2 Avoiding deadlock ........................................... . 42
8 Other communications devices ............................... 43
8.1 Mixing transputer types: the IMS C100 .................................... 43
Contents vii
8.2 Interfacing to peripherals and host systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Software and systems ...................................... 45
9.1 Development software ................................................ . 45
9.1.1 Configuration tools .......................................... . 45
Hardware description ........................................ . 46
Software description ......................................... . 46
Mapping software to hardware ................................. . 46
Configuration languages ...................................... . 46
Types of networks ........................................... . 46
9.1.2 Initializing and loading a network ............................... . 47
Levels of initialization ........................................ . 47
Booting a system from link .................................... . 47
Booting a system from ROM .................................. . 47
9.1 .3 Host servers ................................................ . 47
9.1 .4 Debugging ................................................. . 48
9.1.5 IMS T805 emulation .......................................... . 48
9.2 iq Systems products .................................................. . 48
9.2.1 IMS T9000 products ......................................... . 48
Compatible development products ............................. . 49
IMS T9000 specific products .................................. . 49
Host interfaces ............................................. . 50
10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Part 2: Product Family Preliminary Information ....................... 53
IMS T9000 transputer.. . . . . ... .. .. . . .. . .. .. .. . .. . ... . ... .. . . ... 55
1 Introduction............................................... 56
2 Preliminary pin designations ................................. 58
3 Processor................................................. 60
3.1 Registers ........................................................... . 60
3.2 Processes and concurrency ........................................... . 61
3.3 Priority ............................................................. . 62
3.4 Process types ....................................................... . 63
3.4.1 G-processes: global trap-handling and debugging ................ . 63
3.4.2 L-processes: local error handling and debugging ................. . 64
3.5 Timers 67
3.6 Block move ......................................................... . 68
3.7 Semaphores ........................................................ . 68
4 Communications, events and resources ....................... 69
4.1 Efficient variable-length communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.2 Processor-to-processor communications ................................. 69
viii Contents
4.3 Virtual link control blocks .............................................. . 71
4.3.1 Errors ...................................................... . 71
4.4 VCP and CPU configuration registers .................................... . 72
4.4.1 MemStart register ............................................ . 72
4.4.2 Minimum invalid virtual channel register .......................... . 73
4.4.3 Extemal resource channel base register ......................... . 73
4.4.4 Header area base register ..................................... . 73
4.4.5 Header offset register ........................................ . 73
4.4.6 Packet header limit registers ................................... . 75
4.4.7 VCP command register ....................................... . 75
4.4.8 VCP status register ........................................... . 75
4.4.9 VCP link mode register ....................................... . 75
4.4.10 Event mode register .......................................... . 75
4.5 Events 76
4.6 Resources .......................................................... . 77
5 Memory management ...................... . . . . . . . . . . . . . . . . . 78
5.1 Protection, stack extension, and logical to physical address translation ......... 78
5.2 Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Region descriptors .................................................... 80
5.4 Machine registers ..................................................... 81
5.5 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6 Main Cache ............................................... 82
6.1 Cache instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2 Cache configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7 Programmable memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1 Pin functions ......................................................... 85
7.1.1 ProcClockOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.2 MemDataO-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.3 MemAdd2-31 ................................................ 85
7.1.4 notMemWrBO-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1.5 notMemRASO-3 .............................................. 86
7.1.6 notMemCASO-3 ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1.7 notMemPSO-3............................................... 86
7.1.8 MemWait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1.9 MemReqln, MemGranted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.1.10 MemReqOut ................................................. 87
7.1 .11 notMemBootCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1.12 notMemRf ................................................... 87
7.2 Extemal Bus Cycles ................................................... 88
7.2.1 Extemal DRAM cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.2.2 Extemal non-DRAM cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.2.3 Bank switching. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 92
7.3 PMI configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.3.1 Bank address registers ........................................ 94
Address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Mask registers ............................................... 95