Table Of ContentHybrid Fault Tolerance Techniques to Detect
Transient Faults in Embedded Processors
José Rodrigo Azambuja • Fernanda Kastensmidt
Jürgen Becker
Hybrid Fault Tolerance
Techniques to Detect
Transient Faults
in Embedded Processors
1 3
José Rodrigo Azambuja Jürgen Becker
Centro de Ciências Computacionais Institut für Technik der
Federal University of Rio Grande Informationsverarbeitung
Rio Grande Karlsruhe Institute of Technology
Brazil Karlsruhe
Germany
Fernanda Kastensmidt
Instituto de Informática
Federal University of Rio Grande do Sul
Porto Alegre
Brazil
ISBN 978-3-319-06339-3 ISBN 978-3-319-06340-9 (eBook)
DOI 10.1007/978-3-319-06340-9
Springer Cham Heidelberg New York Dordrecht London
Library of Congress Control Number: 2014941949
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Preface
Recent technology advances have provided faster and smaller devices for manufac-
turing circuits that while more efficient have become more sensitive to the effects
of radiation. Smaller transistor dimensions, higher density integration, lower volt-
age supplies and higher operating frequencies are some of the characteristics that
make energized particles an issue when dealing with integrated circuits in harsh
environments. These types of particles have a major influence in processors work-
ing in such environments, affecting both the program’s execution flow by causing
incorrect jumps in the program, and the data stored in memory elements, such as
data and program memories, and registers. In order to protect processor systems,
fault tolerance techniques have been proposed in literature using hardware-based
and software-based approaches, which decrease the system’s performance, increase
its area, and are not able to fully protect the system against such effects. In this
context, we proposed a combination of hardware- and software-based techniques to
create hybrid techniques aimed at detecting all the faults affecting the system, at low
performance degradation and memory overhead. Five techniques are presented and
described in detail, from which two are known software-based only techniques and
three are new hybrid techniques, to detect all kinds of transient effects caused by
radiation in processors. The techniques are evaluated according to execution time,
program and data memories, and area overhead and operating frequency degrada-
tion. To verify the effectiveness and the feasibility of the proposed techniques, fault
injection campaigns are performed by injecting faults by simulation and performing
irradiation experiments in different locations with neutrons and a Cobalt-60 sourc-
es. Results have shown that the proposed techniques improve the state-of-the-art
by providing high fault detection rates at low penalties on performance degradation
and memory overhead.
v
Acknowledgements
I would like to start by thanking my parents, Tais and Gui, and my brother, Cado,
who have always been there for me, being “there” a few meters, or a few thousand
kilometers away. Thank you for all the support you provided me, allowing me to de-
vote myself entirely to the studies. I also thank my grandparents, uncles and cousins
for the countless moments, which would not fit in these few lines.
I take the opportunity also to thank Georg, who despite not having any kind of
kinship with me was like a second father during the time I spent in Germany.
I would also like to thank my colleagues from UFRGS, Anelise, Carol, Ed-
uardo, Fernando, Jimmy, Jorge, Lucas, Samuel, William and Mauricio, for the
countless hours discussing a variety of subjects, the chimarrões, and the terrible
football championships (and let there be Radecs!), and from KIT, Christoph, Fal-
co, Mahtab and Oliver, for the indoor sports, FPGA boards resuscitation and hat
making.
To all my friends who took me out of the lab during the weekends—and also to
the ones who kept me in it during the week—and my apologies for not being able
to quote you all. To FDC, for all the poorly planned adventures, and to the band, for
not letting rock die—and still allowing me to play in it.
To the great friends who I rediscovered and to the great friendships I made during
my stay in Germany, who made my day much better and my job much easier, Ari,
Bruna, Cilene, Cláudio, Elian, Fada, Irigas, Paola, Pedrão, Gabriel, Oliver, Sharon,
and Zatt, and to those who I barely saw in person, but have always been fighting evil
with me in the fields of justice, Christoph, Dirk, Fabio and Julian.
To my entrepreneurs friends who came to believe in a small project and today are
richer than Eike Batista: Inácio and Werner.
Especially to Fernanda, for putting up with me during 7 years. Thank you for the
confidence and freedom of research on the most varied subjects. I also thank Pro-
fessor Jürgen Becker for the many research opportunities inside—and outside—of
KIT, as well as for providing me with a great work environment. To Professors
Álvaro, Lisboa, Luigi, Michael, Paolo, Reis and Weber, for all their help during
my PhD.
vii
viii Acknowledgements
To Elisiane, Leivo and to the coordination of PPGC, Instituto de Informática,
ITIV, UFRGS, and KIT and to the financial support provided by CNPq, CAPES
and HIRST.
Finally, I would like to thank the supernatural forces—in which I do not believe,
but I know they exist—that make us go forward and until the end.
To all of you, my sincere Thanks.
Contents
1 Introduction ................................................................................................ 1
1.1 Motivation and Problem Definition .................................................... 2
1.2 Overview ............................................................................................. 4
2 Background ............................................................................................... 7
2.1 Basic Concepts of Dependable and Secure Computing ...................... 7
2.1.1 Defect, Upset and Fault Definitions ........................................ 7
2.1.1.1 Single Event Effect (SEE) ........................................ 8
2.1.1.2 Total Ionizing Dose (TID) ........................................ 9
2.1.2 Error and Failure Definitions .................................................. 9
2.2 MIPS Architecture ............................................................................... 12
2.3 SEE in MIPS Processors ..................................................................... 14
2.3.1 SEEs Divided by Sensitive Areas of a Processor .................... 14
2.3.2 SEEs Divided by Effect on a Processor .................................. 15
2.4 Fault Injection and Testing .................................................................. 16
2.4.1 Fault Injection by Simulation .................................................. 16
2.4.2 FPGA Memory Configuration Bitstream Fault Injection........ 17
2.4.3 Irradiation Experiments ........................................................... 18
3 Fault Tolerance Techniques for Processors ............................................ 19
3.1 Software-Based Techniques ................................................................ 21
3.2 Hardware-Based Techniques ............................................................... 23
3.3 Hybrid Techniques .............................................................................. 26
3.4 Summary ............................................................................................. 28
4 Proposed Techniques to Detect Transient Faults in Processors ............ 29
4.1 Hardening Post Compiling Tool (HPCT) ............................................ 29
4.2 Improved Variables Technique (VAR) ................................................ 31
4.2.1 Implementation Details ........................................................... 32
4.3 Improved Inverted Branches Technique (BRA) .................................. 34
4.3.1 Implementation Details ........................................................... 34
ix
x Contents
4.4 PODER Technique .............................................................................. 36
4.4.1 Software-Based Side ............................................................... 37
4.4.1.1 Jumps to the Beginning of a Basic Block ................ 38
4.4.1.2 Jumps to the Same Basic Block ............................... 39
4.4.2 Hardware-Based Side .............................................................. 40
4.4.3 Implementation Details ........................................................... 41
4.4.3.1 PODER’s Software Transformation
Implementation ........................................................ 41
4.4.3.2 Hardware Module Implementation .......................... 44
4.5 On-line Control Flow Checker Module (OCFCM) ............................. 45
4.5.1 Hardware-Based Side .............................................................. 47
4.5.2 Software-Based Side ............................................................... 48
4.5.3 Implementation ....................................................................... 49
4.6 Hybrid Error-Detection Technique Using Assertions ......................... 51
4.6.1 Terminology ............................................................................ 52
4.6.2 Software-Based Side ............................................................... 53
4.6.2.1 Description Details ................................................... 54
4.6.2.2 Signature Checking Algorithms ............................... 55
4.6.3 Hardware-Based Side .............................................................. 57
4.6.4 Implementation Details ........................................................... 58
4.6.4.1 HETA Software Transformation .............................. 58
4.6.4.2 Hardware Module Implementation .......................... 60
5 Simulation Fault Injection Experimental Results .................................. 63
5.1 PODER ................................................................................................ 65
5.2 OCFCM ............................................................................................... 66
5.3 HETA ................................................................................................... 67
6 Configuration Bitstream Fault Injection Experimental Results .......... 69
6.1 PODER ................................................................................................ 71
6.2 OCFCM ............................................................................................... 72
6.3 HETA ................................................................................................... 73
7 Radiation Experimental Results ............................................................... 75
7.1 MIPS in Flash-Based FPGAS ............................................................. 75
7.1.1 TID Experiment ...................................................................... 76
7.1.2 Neutron Experiment ................................................................ 79
7.2 MIPS in SRAM-Based FPGAS .......................................................... 80
7.2.1 T ID Experiment ...................................................................... 80
7.2.2 Neutron Experiment ................................................................ 81
8 Conclusions and Future Work .................................................................. 85
References ......................................................................................................... 89
Index .................................................................................................................. 93
List of Abbreviations and Acronyms
ACCE Automatic Correction of Control Flow Errors
ACCED Automatic Correction of Control Flow Errors with Duplication
ALU Arithmetic and Logic Unit
ASIC Application Specific Integrated Circuits
AUT Area Under Test
BB Basic Block
BID Block Identifier
BRA Inverted Branches Technique
BRAM Block Random Access Memory
CAEN Chemically Assembled Electronic Nanotechnology
CCA Control Flow Checking using Assertions
CEDA Control-flow Error Detection through Assertions
CFCSS Control Flow Checking by Software Signatures
CFID Control Flow Identifier
CLB Configurable Logic Block
COTS Commercial Off The Shelf
CUDA Compute Unified Device Architecture
CUT Circuit Under Test
CWSP Code Word State Preserving
DUT Design Under Test
DWC Duplication With Comparison
ECC Error Correcting Codes
ECCA Enhanced Control Flow Checking using Assertions
EDAC Error Detection And Correction
ED4I Error Detection by Data Diversity and Duplicated Instructions
EHP Electron-Hole-Pairs
ENSERG Ecole Nationale Supérieure d'Electronique et de Radioélectricité de
Grenoble
EoE End of Execution
FIT Failure In Time
FF Flip-Flop
FP Frame Pointer
xi
