Table Of ContentWilliam Fornaciari · Dimitrios Soudris
Editors
Harnessing
Performance Variability
in Embedded and High-
performance Many/
Multi-core Platforms
A Cross-layer Approach
Harnessing Performance Variability in Embedded
and High-performance Many/Multi-core Platforms
William Fornaciari • Dimitrios Soudris
Editors
Harnessing Performance
Variability in Embedded and
High-performance
Many/Multi-core Platforms
A Cross-layer Approach
123
Editors
WilliamFornaciari DimitriosSoudris
DEIB–DipartimentodiElettronica SchoolofElectrical&Comp.Engineering
InformazioneeBioingegneria Natl.TechnicalUniv.ofAthens
PolitecnicodiMilano Athens,Greece
Milano,Italy
ISBN978-3-319-91961-4 ISBN978-3-319-91962-1 (eBook)
https://doi.org/10.1007/978-3-319-91962-1
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Introduction
Thisbookaimsatprovidingacomprehensiveviewofthepossiblesolutionstothe
problemofensuringdependableperformance,bycollectingthebestpracticesfrom
theembeddedandhigh-performanceworlds.Thereexistsabroadrangeofpossible
sourcesofperformancevariability,spanningfromthehardware(silicon)aspectsup
to the design of the applicationsandthe managementof the resources.To worsen
the scenario, it is no longer possible to underestimate the impact of power and
thermalmanagementandofprocessvariation,especiallyintheperspectivetodeal
with reliability and aging issues. The goal of this book is to share the experience
maturated during the HARPA project and to complement such information with
backgroundconceptsandchapters,tocreateascientificreferenceforbothacademic
andleading-edgecompanies.
The HARPA project’s goal has been to enable next-generation embedded and
high-performanceheterogeneousmany-coreprocessorstocost-effectivelyconfront
variationsandyetprovidedependableperformance:correctfunctionalityandtiming
guarantees throughout the expected lifetime of a platform under thermal, power,
and energy constraints. The HARPA team is composed of industry and academic
partnersacrossEuropespecializedinfieldscoveringalltheabstractionlayers,from
hardware to application level. One of the primary objectives of HARPA project
is accomplished by means of an accurate yet efficient modeling of performance
variabilityinscaledtechnologies.Capturingandsimulatingvariabilitythreatsisan
importantsteptowardprovidingsolutionsinmitigatingthem.
The HARPA solutionrevolvesarounda cross-layerapproachencompassingall
pertinentactors in the system stack. At the core of HARPA, a middleware imple-
ments an innovative control engine that steers software/hardware knobs based on
informationfrommonitorsstrategicallydispersedinthesystem.Wehaveexplored
a large range of such knobs and monitors across differentabstraction levels. This
enginereliesontechnologymodelstoidentifyandexploitvarioustypesofplatform
slack—such as performance, power, energy, temperature, lifetime, and structural
(i.e.,hardware)—torestorethetimingguaranteesandensureexpectedlifetimeinthe
presence of time-dependentvariations. The challenge of dependable performance
v
vi Introduction
is to ensure timing correctness, whereas for high-performance applications it is
paramounttoensureloadbalancingduringparallelphasesandfastexecution.Both
areachievedwithacombinationofafastcontrolenginewithreactiontimesinthe
rangeofa fewmsec andan OS-levelenginereactingslower.Theseconceptshave
beendemonstratedinthreedifferentrepresentativeapplicationcasestudiesfromthe
wireless,floodmonitoring,androckfallmonitoringdomains.
Among different variability phenomena, attention is given to the BTI effects,
since they are expected to be the dominant ones. For this purpose, a proper
estimationflowthatmodelsthedependenceofvariabilityatcircuitandblocklevel
on the operating conditions (temperature and voltage), workload, and technology
parameters has been designed and developed. Experimental results have shown
running different application benchmarks of interest. The flow is based on com-
mercialASICtoolsandin-housescripts:fromthetransistor-levelrepresentationof
thecircuit,andthe transistor-level(real)workload,BTI variationbasedondefect-
centricmodelsisquantified,anditsimpactonthecriticalpathdelayofthereference
circuitisthenanalyzedthroughstandardSTArun.
Although the impact on BTI is driven by the trends in current technology, the
system-levelperspectiveis a jointresult of differentfailure mechanisms.To close
the gap with system-level analysis, an experimentalsetup to measure the impacts
ofstress-inducedvariabilityatthesystemlevel,fromafunctionalperspective,has
been designed and deployed. The proposed setup allows us to directly measure
fromthehardwarethetimebetweensuccessivefaults.Whilemodelinganddeeply
understanding variability impact is an important part of the work, a fundamental
objective of the project is to provide solutions to mitigate reliability threats and
ensuredependablesystemperformance.Towardthisdirection,theHARPA engine
has been developed, implementing various control frameworks across the system
stack.Thegoalistoexploitdifferentmanifestationsofplatformslack(i.e.,slackin
performance,power, energy,temperature,lifetime, and structures/components),in
ordertoascertaintimingguaranteesthroughoutthelifetimeofthedevice.
The reader is steered into the concept developed during the project passing
throughthreemainstages:backgroundconcepts,designmethodologies,andanaly-
sisofusecases.Tosimplifythenavigationofthebooktothereader,thediscussion
isfurthersplitinto6partsandfinally13agilechapters.
Thebeginningofthefirstpartisanintroductorychapterprovidinganoverview
ofthetargetproblemsandoftheapproachtotheirmitigationdevelopedduringthe
HARPAproject,whichisasortofreferenceguidetomoveintothebookconcepts
and chapters. The other two chapters of the first part provide a background on
theevolutionofthe computingplatforms,with a particularfocusontheprocessor
architectures and some foundations on the aging effects from the physics of the
phenomenonuptotheCADaspects.
Thesecondpartstartsenteringintotherun-timemanagementtechnologieswith
two chaptersexplainingfirst of all the solutionsworkingat the operatingsystems
level and then how to cope with the problem to achieve a fast and low overhead
thermalcontrolofmulti-manycoreprocessors.
Introduction vii
Thefollowingtwochapters,constitutingthethirdpart,moveintoafinergrainof
the design consideringthe RT leveland how to design an ad hoc run-timeengine
to deal with real-time performance requirements. A comprehensive view of the
monitorsandknobsistheobjectiveofthefourthpartofthebook,focusingonboth
the system-level solutions and on a specific new brick of the emergingplatforms,
namely, the Network-on-Chip. A coordinated application of the background and
conceptspresentedsofariscarriedoutinthetwochapterscomposingthefifthpart
of the book. The first of them is affording the problem of properly modeling and
simulating BTI-induced degradation in the computing platform and its impact on
the timing performance,while the second is the description of a proofof concept
performedonarealplatform.
Thefinalpartofthebookfiguresouthowthemethodologiesandtechniqueshere
presentedcanbeeffectivelyappliedonreal-sizeproblems.Tothispurpose,twouse
casesoutofthethreedevelopedduringtheHARPAprojectarepresented:Floreon+
toshowthepossiblebenefitsachievableonapplicationandarchitecturesbelonging
to the high-performancecomputing domain and Beesper, which is a typical low-
end embedded system submitted to severe reliability and energy management
constraints.
Thisbookisprobablythefirst onetryingto coverallthe criticalaspectsofthe
computingcontinuumand,aswesaid,iswellsuitedbothforengineersworkingin
leading-edgecompaniesandforcoursesatthemaster’sandPhDlevel.
Special thanks to Antonio Gonzalez and Jörg Henkel for their availability to
cooperate with us in this project, writing two excellent chapters of the book and
withthehopetoextendinthefuturethescientificcooperationonnewchallenges.
Wehopeyouwillenjoyreadingthebook,astheauthorsenthusiasticallyworked
togetherfor4years.
Milano,Italy WilliamFornaciari
Athens,Greece DimitriosSoudris
Contents
1 TheHARPAApproachtoEnsureDependablePerformance.......... 1
Nikolaos Zompakis, Michail Noltsis, Panagiota Nikolaou,
PanayiotisEnglezakis,ZachariasHadjilambrou,LorenaNdreu,
GiuseppeMassari,SimoneLibutti,AntoniPortero,FedericoSassi,
AlessandroBacchini,ChrysostomosNicopoulos,YiannakisSazeides,
Radim Vavrik,Martin Golasowski,Jiri Sevcik,StepanKuchar,
Vit Vondrak,Fritsch Agnes, HansCappelle, FranckyCatthoor,
WilliamFornaciari,andDimitriosSoudris
PartI
2 TrendsinProcessorArchitecture......................................... 23
AntonioGonzález
3 AgingEffects:FromPhysicstoCAD..................................... 43
HussamAmrouch,HebaKhdr,andJörgHenkel
PartII OSLayer
4 TheHARPA-OS ............................................................ 73
SimoneLibutti,GiuseppeMassari,andWilliamFornaciari
5 Event-Based Thermal Control for High Power Density
Microprocessors ............................................................ 107
FedericoTerraneo,AlbertoLeva,andWilliamFornaciari
PartIII HARPA-RTLayer
6 HARPART.................................................................. 131
Dimitrios Rodopoulos,Nikolaos Zompakis, Michail Noltsis,
FranckyCatthoor,andDimitriosSoudris
ix
x Contents
7 Improving Robustness of a Real-Time SpectrumSensing
ApplicationwiththeHARPARun-TimeEngine........................ 151
HansCappelle,MichailNoltsis,SimoneCorbetta,
andFranckyCatthoor
PartIV KnobsandMonitors
8 EvaluatingSystem-LevelMonitorsandKnobsonRealHardware... 167
PanagiotaNikolaou,ZachariasHadjilambrou,PanayiotisEnglezakis,
LorenaNdreu,ChrysostomosNicopoulos,YiannakisSazeides,
AntoniPortero,RadimVavrik,andVitVondrak
9 MonitorandKnobTechniquesinNetwork-on-ChipArchitectures .. 187
Davide Zoni, Panayiotis Englezakis, Kypros Chrysanthou,
Andrea Canidio, Andreas Prodromou, Andreas Panteli,
Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos,
YiannakisSazeides,andWilliamFornaciari
PartV TechnologyRelatedReliabilityApproach
10 Time-EfficientModelingandSimulationofTrueWorkload
DependencyforBTI-InducedDegradationinProcessor-Level
PlatformSpecifications..................................................... 217
Simone Corbetta, Pieter Weckx, Dimitrios Rodopoulos,
DimitriosStamoulis,andFranckyCatthoor
11 Proof-of-ConceptHARPA Measurement-BasedPlatform
ModellingFramework ..................................................... 237
SimoneCorbetta,WimMeeus,EtienneCappe,FranckyCatthoor,
andAgnesFritsch
PartVI Applications
12 Floreon+ Modules:AReal-WorldHARPAApplicationinthe
High-EndHPCSystemDomain .......................................... 265
AntoniPortero,Radim Vavrik,MartinGolasowski, JiriSevcik,
Giuseppe Massari, Simone Libutti, William Fornaciari,
StepanKuchar,andVitVondrak
13 BeesperSmartBridge:AReal-WorldHARPAApplicationin
theLow-EndEmbeddedSystemDomain................................ 295
FedericoSassi,AlessandroBacchini,andGiuseppeMassari
Index............................................................................... 319
Chapter 1
The HARPA Approach to Ensure
Dependable Performance
NikolaosZompakis,MichailNoltsis,PanagiotaNikolaou,
PanayiotisEnglezakis,ZachariasHadjilambrou,LorenaNdreu,
GiuseppeMassari,SimoneLibutti,AntoniPortero,FedericoSassi,
AlessandroBacchini,ChrysostomosNicopoulos,YiannakisSazeides,
RadimVavrik,MartinGolasowski,JiriSevcik,StepanKuchar,VitVondrak,
FritschAgnes,HansCappelle,FranckyCatthoor,WilliamFornaciari,
andDimitriosSoudris
1.1 Introduction
The evolution towards processors with heterogeneous many-cores is impeded by
variability related challenges. This is primarily due to increasing susceptibility to
static [3] and dynamic [4] variations in the performance and leakage energy of
the silicon devices and wires. Static variations are due to imperfections in the
fabrication process, such as line-edge roughness and random dopant fluctuations,
whereasdynamiconesareduetotime-dependentvariations,suchasaging,ambient
N.Zompakis·M.Noltsis·D.Soudris
MicroLab-ECE-NTUA,Athens,Greece
e-mail:[email protected];[email protected];[email protected]
P.Nikolaou·P.Englezakis((cid:2))·Z.Hadjilambrou·L.Ndreu·C.Nicopoulos·Y.Sazeides
UniversityofCyprus,Nicosia,Cyprus
e-mail:[email protected];[email protected];
[email protected];[email protected];[email protected];[email protected]
G.Massari·S.Libutti·W.Fornaciari
DEIBPolitecnicodiMilano,Milano,Italy
e-mail:[email protected];[email protected];[email protected]
A.Portero·R.Vavrik·M.Golasowski·J.Sevcik·S.Kuchar·V.Vondrak
IT4Innovations,Ostrava-Poruba,TheCzechRepublic
e-mail:[email protected];[email protected];[email protected];
[email protected];[email protected];[email protected]
F.Sassi·A.Bacchini
CamlinItalys.r.l.,Parma,PR,Italy
e-mail:[email protected];[email protected]
©SpringerInternationalPublishingAG,partofSpringerNature2019 1
W.Fornaciari,D.Soudris(eds.),HarnessingPerformanceVariability
inEmbeddedandHigh-performanceMany/Multi-corePlatforms,
https://doi.org/10.1007/978-3-319-91962-1_1
