First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate

119 Pages·2017·0.68 MB·English

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LSU Master's Theses Graduate School
2004
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Syam Prasad SBS Kommana
Louisiana State University and Agricultural and Mechanical College
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Kommana, Syam Prasad SBS, "First order sigma-delta modulator of an oversampling ADC design in
CMOS using floating gate MOSFETS" (2004). LSU Master's Theses. 3638.
https://digitalcommons.lsu.edu/gradschool_theses/3638
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FIRST ORDER SIGMA-DELTA MODULATOR OF AN
OVERSAMPLING ADC DESIGN IN CMOS USING
FLOATING GATE MOSFETS

A Thesis

Submitted to the Graduate Faculty of the
Louisiana State University and
Agricultural and Mechanical College
in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering

in

The Department of Electrical and Computer Engineering

by
Syam Prasad SBS Kommana
Bachelor of Technology, Nagarjuna University, 2001
December 2004
Acknowledgments

I would like to take this opportunity to thank everyone who contributed to the
successful completion of this thesis. First of all, I would like to thank Dr. Ashok
Srivastava, my major professor, for providing extensive support and encouragement
throughout this work. I would also like to thank Dr. Martin Feldman and Dr. Subhash
Kak for being a part of my committee.
I am very thankful to the Department of Electrical and Computer Engineering and
Center for Computation & Technology for supporting me financially during my stay at
LSU.
I would like to thank my parents Prabhavathi and Murali Krishna and to all my
family members and friends for their constant prayers and moral support throughout my
life. I deeply thank my mother for her efforts to make me successful. Special thanks to
my brother, sisters and brother-in-laws for all their love and support.
I also thank Anand for his help in my work and all my other friends, Satish,
Pavan, Harish, Chandra, Subhakar, Sunil, and Kasyap for their help and encouragement
at times I needed them. I also thank all my friends at LSU who helped me indirectly in
my work.
Last of all I thank GOD for keeping me in good health and spirits throughout my
stay at LSU.
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Table of Contents

Acknowledgments.............................................................................................................ii

List of Tables.....................................................................................................................v

List of Figures...................................................................................................................vi

Abstract.............................................................................................................................ix

Chapter 1
Introduction.......................................................................................................................1
1.1 Introduction.........................................................................................................1
1.2 Literature Review................................................................................................9
1.3 Chapter Organization........................................................................................11

Chapter 2
Multi Input Floating Gate (MIFG) MOSFETS...........................................................14
2.1 Introduction.......................................................................................................14
2.2 Structure of MIFG MOSFET and Device Physics...........................................14
2.3 Floating Gate CMOS Inverter...........................................................................16
2.4 Unit Capacitance...............................................................................................20
2.5 Design Issues....................................................................................................24

Chapter 3
Sigma Delta A/D Converter Architecture and Operation...........................................25
3.1 Quantization and Sampling...............................................................................25
3.2 Analog-to-Digital Converter Types..................................................................29
3.2.1 Oversampling ADC Architecture.............................................................32
3.3 Delta Modulation..............................................................................................35
3.4 Comparison of Different Architectures............................................................36
3.5 The First Order Sigma-Delta Modulator...........................................................41
3.5.1 Design of Integrator..................................................................................42
3.5.2 Design of Operational Amplifier with Floating Gates at Input Stage..49
3.5.3 Design of Comparator...............................................................................62
3.5.4 1-bit Digital-to-Analog Converter............................................................65
3.6 Implementation and Analysis of Modulator.....................................................67

Chapter 4
Theoretical and Experimental Results..........................................................................72

Chapter 5
Conclusion.......................................................................................................................93

References........................................................................................................................94

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Appendix A
Spice Parameters from [25]............................................................................................97

Appendix B
Simulating Floating Gate MOS Transistor..................................................................98

Appendix C
Decimator Implementation..........................................................................................102

Appendix D
Testing the Chip (IC # T37C-BS)................................................................................103

Vita.................................................................................................................................109
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List of Tables

Table 1.1: Comparison of op-amps using floating gate MOSFETs..................................12

Table 1.2: Comparison of characteristics of different ADC architectures........................13

Table 3.1: Classification of ADC architectures................................................................30

Table 3.2: Comparison of the performance characteristics for four major ADC
architectures…………………………………………………………………..40

Table 3.3: Specifications of the simulated op-amp using post-layout spice simulations.58

Table 4.1: Input and measured output from the designed ADC.......................................83

Table D.1 gives the pin numbers and their description to test 1st order modulator........106
v
List of Figures

Figure 1.1: Floating-gate MOSFET....................................................................................2

Figure 1.2: (a) Block diagram of Nyquist rate converters [10]...........................................5

Figure 1.2: (b) Block diagram of oversampling ADCs [10]...............................................5

Figure 1.3: Block diagram of a sigma-delta ADC [11].....................................................6

Figure 1.4: Block diagram of a 1st order modulator [12]....................................................7

Figure 2.1: Basic structure of a multi-input floating gate MOSFET................................17

Figure 2.2: Terminal voltages and coupling capacitances of a multi-input floating gate
MOSFET.........................................................................................................18

Figure 2.3: (a) MIFG p-MOSFET. (b) MIFG n-MOSFET...............................................19

Figure 2.4: Multi-input floating gate (MIFG) CMOS inverter.........................................21

Figure 2.5: The capacitive network for a multi-input floating gate CMOS inverter [24].22

Figure 2.6: Transfer characteristics of a 4-input floating gate CMOS inverter................23

Figure 3.1: Block diagram of general ADC [29]..............................................................26

Figure 3.2: (a) Continuous time frequency response of the analog input signal. (b)
Sampled-data equivalent frequency response. (c) Case where f > 0.5f ,
B S
causing aliasing. (d) Use of an anti-aliasing filter to avoid aliasing. (e)
Frequency domain of oversampling converter [29]........................................28

Figure 3.3: Oversampled sigma-delta ADC......................................................................33

Figure 3.4 (a): Delta Modulation and Demodulation........................................................37

Figure 3.4 (b): Delta Modulation waveforms [33]............................................................37

Figure 3.5: Block diagram of a first order sigma-delta modulator...................................43

Figure 3.6: Pulse density output from a sigma-delta modulator for a sine wave input….44

Figure 3.7: A conventional noninverting integrator.........................................................46

Figure 3.8: Timing diagram for the two clock signals......................................................47

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Figure 3.9: Block diagram of a two stage op-amp with output buffer..............................50

Figure 3.10: Circuit Diagram of a two-stage CMOS operational amplifier.....................52

Figure 3.11: A floating gate MOS differential pair [38]...................................................54

Figure 3.12: Building blocks using MIFG transistors [22]...............................................55

Figure 3.13: Transfer characteristics of op-amp circuit of Fig. 3.9 obtained from
post-layout simulations................................................................................59

Figure 3.14: Transient analysis of op-amp circuit of Fig. 3.9 obtained from post-layout
simulations...................................................................................................60

Figure 3.15: Frequency response of op-amp circuit of Fig. 3.9 obtained from post-layout
simulations....................................................................................................61

Figure 3.16: Circuit diagram of a CMOS comparator using floating gate MOSFETs.....63

Figure 3.17: Circuit diagram of an 1-bit DAC..................................................................66

Figure 3.18: Sampled data model of a first order sigma-delta modulator........................68

Figure 3.19: A complete first-order sigma-delta modulator.............................................70

Figure 3.20: Circuit diagram of a first order modulator with floating gate MOSFETs....71

Figure 4.1: CMOS chip layout of a first order sigma delta modulator using floating gate
transistors.......................................................................................................73

Figure 4.2: CMOS chip layout of a 1st order sigma delta modulator in a pad frame of 2.25
mm × 2.25 mm size.........................................................................................74

Figure 4.3: Microphotograph of the fabricated 1st order modulator chip.........................75

Figure 4.4: Microphotogrpah of the modulator part in fabricated chip............................76

Figure 4.5: SPICE simulation results of a 1-bit modulator (ADC)..................................78

Figure 4.6: Measured 1-bit digital output from the fabricated chip..................................79

Figure 4.7 (a): Measured digital output (10110100) ≡ 1.0156 V of an integrated 8-bit
2
sigma-delta ADC for an anlaog input of 1 V...................................................80

Figure 4.7 (b): Measured digital output (11011001) ≡ 1.7382 V of an integrated 8-bit
2
sigma-delta ADC for an anlaog input of 1.7 V................................................81
vii
Figure 4.7 (c): Measured digital output (00101011) ≡ -1.7382 V of an integrated 8-bit
2
sigma-delta ADC for an analog input of -1.7 V...............................................82

Figure 4.8: The layout for sc-integrator............................................................................85

Figure 4.9: The output characteristics of post layout simulation of the integrator of
Fig. 4.8............................................................................................................86

Figure 4.10: The layout for comparator using floating gate transistors............................87

Figure 4.11: Post layout simulation output characteristics of the comparator of
Fig 4.10.........................................................................................................88

Figure 4.12: Measured output characteristics of comparator of Fig. 4.10........................89

Figure 4.13: Layout of DAC.............................................................................................90

Figure 4.14: The post layout simulated output characteristics of DAC of Fig. 4.13........91

Figure 4.15: Measured output characteristics of DAC of Fig. 4.13..................................92

Figure B.1: Equivalent circuit of a multi-input floating-gate inverter for electrical
simulations.....................................................................................................99

Figure B.2: Resistor added to equivalent circuit for simulation purposes......................100

Figure C.1: Experimental set-up for the first-order sigma-delta modulator...................102

Figure D.1: Pin assignment for the chip layout..............................................................104

Figure D.2: Chip layout .................................................................................................105
viii
Abstract

We report a new architecture for a sigma-delta oversampling analog-to-digital
converter (ADC) in which the first order modulator is realized using the floating gate
MOSFETs at the input stage of an integrator and the comparator. The first order
modulator is designed using an 8 MHz sampling clock frequency and implemented in a
standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is
programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA
board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth.
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