ESD Basics: From Semiconductor Manufacturing to Product Use

219 Pages·2012·8.104 MB·English

by  Steven H. Voldman(auth.), Steven H. Voldman(eds.)

ESD BASICS
ESD Series
By Steven H. Voldman
ESDBasics:FromSemiconductorManufacturingtoProductUse
ISBN:9780470979716
September2012
ESD:DesignandSynthesis
ISBN:9780470685716
March2011
ESD:FailureMechanismsandModels
ISBN:9780470511374
July2009
Latchup
ISBN:9780470016428
December2007
ESD:RFTechnologyandCircuits
ISBN:9780470847558
September2006
ESD:CircuitsandDevices
ISBN:9780470847541
November2005
ESD:PhysicsandDevices
ISBN:9780470847534
September2004
Upcomingtitles:
ESD:TestandCharacterization
ElectricalOverstress(EOS):Devices,Circuits,andSystems
TheESDHandbook
ESD BASICS
From Semiconductor
Manufacturing to Product Use
Steven H. Voldman
IEEE Fellow, Vermont, USA
Thiseditionfirstpublished2012
#2012JohnWiley&Sons,Ltd
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LibraryofCongressCataloging-in-PublicationData
Voldman,StevenH.
ESDbasics:fromsemiconductormanufacturingtoproductuse/StevenVoldman.
p.cm.
Includesbibliographicalreferencesandindex.
ISBN978-0-470-97971-6(hardback)
1. Electronicapparatusandappliances–Designandconstruction. 2. Electricdischarges. 3. Electronic
apparatusandappliances–Protection. 4. Microelectronics. 5. Staticeliminators. 6. Electrostatics. I.Title.
TK7836.V652012
621.3815–dc23 2012018125
AcataloguerecordforthisbookisavailablefromtheBritishLibrary.
PrintISBN:9780470979716
Setin10/12pt,TimesbyThomsonDigital,Noida,India.
To My Parents
Carl and Blossom Voldman
Contents
AbouttheAuthor xiii
Preface xv
Acknowledgments xvii
1 FundamentalsofElectrostatics 1
1.1 Introduction 1
1.2 Electrostatics 1
1.2.1 ThalesofMiletusandElectrostaticAttraction 2
1.2.2 ElectrostaticsandtheTriboelectricSeries 3
1.2.3 TriboelectricSeriesandGilbert 4
1.2.4 TriboelectricSeriesandGray 4
1.2.5 TriboelectricSeriesandDufay 4
1.2.6 TriboelectricSeriesandFranklin 5
1.2.7 Electrostatics–SymmerandtheHumanBodyModel 5
1.2.8 Electrostatics–CoulombandCavendish 5
1.2.9 Electrostatics–FaradayandtheIcePailExperiment 5
1.2.10 Electrostatics–FaradayandMaxwell 6
1.2.11 Electrostatics–Paschen 6
1.2.12 Electrostatics–Stoneyandthe“Electron” 6
1.3 TriboelectricCharging–HowdoesitHappen? 7
1.4 Conductors,Semiconductors,andInsulators 8
1.5 StaticDissipativeMaterials 8
1.6 ESDandMaterials 9
1.7 ElectrificationandCoulomb’sLaw 9
1.7.1 ElectrificationbyFriction 10
1.7.2 ElectrificationbyInduction 10
1.7.3 ElectrificationbyConduction 10
1.8 ElectromagnetismandElectrodynamics 11
1.9 ElectricalBreakdown 11
1.9.1 ElectrostaticDischargeandBreakdown 11
1.9.2 BreakdownandPaschen’sLaw 12
1.9.3 BreakdownandTownsend 12
viii CONTENTS
1.9.4 BreakdownandToepler’sLaw 13
1.9.5 AvalancheBreakdown 13
1.10 ElectroquasistaticsandMagnetoquasistatics 15
1.11 ElectrodynamicsandMaxwell’sEquations 16
1.12 ElectrostaticDischarge(ESD) 16
1.13 ElectromagneticCompatibility(EMC) 16
1.14 ElectromagneticInterference(EMI) 16
1.15 SummaryandClosingComments 17
References 17
2 FundamentalsofManufacturingandElectrostatics 21
2.1 Materials,Tooling,HumanFactors,andElectrostaticDischarge 22
2.1.1 MaterialsandHumanInducedElectricFields 23
2.2 ManufacturingEnvironmentandTooling 23
2.3 ManufacturingEquipmentandESDManufacturingProblems 23
2.4 ManufacturingMaterials 24
2.5 MeasurementandTestEquipment 24
2.5.1 ManufacturingTestingforCompliance 25
2.6 GroundingandBondingSystems 27
2.7 Worksurfaces 27
2.8 WristStraps 28
2.9 ConstantMonitors 28
2.10 Footwear 28
2.11 Floors 28
2.12 PersonnelGroundingwithGarments 29
2.12.1 Garments 29
2.13 AirIonization 29
2.14 Seating 29
2.15 Carts 30
2.16 PackagingandShipping 31
2.16.1 ShippingTubes 31
2.16.2 Trays 32
2.17 ESDIdentification 32
2.18 ESDProgramManagement–TwelveStepstoBuildinganESDStrategy 32
2.19 ESDProgramAuditing 33
2.20 ESDOn-ChipProtection 33
2.21 SummaryandClosingComments 34
References 34
3 ESD,EOS,EMI,EMCandLatchup 39
3.1 ESD,EOS,EMI,EMCandLatchup 39
3.1.1 ESD 39
3.1.2 EOS 40
3.1.3 EMI 40
3.1.4 EMC 41
3.1.5 Latchup 41
CONTENTS ix
3.2 ESDModels 41
3.2.1 HumanBodyModel(HBM) 41
3.2.2 MachineModel(MM) 43
3.2.3 CassetteModel 45
3.2.4 ChargedDeviceModel(CDM) 46
3.2.5 TransmissionLinePulse(TLP) 46
3.2.6 VeryFastTransmissionLinePulse(VF-TLP) 50
3.3 ElectricalOverstress(EOS) 50
3.3.1 EOSSources–Lightning 51
3.3.2 EOSSources–ElectromagneticPulse(EMP) 52
3.3.3 EOSSources–Machinery 52
3.3.4 EOSSources–PowerDistribution 52
3.3.5 EOSSources–Switches,RelaysandCoils 53
3.3.6 EOSDesignFlowandProductDefinition 53
3.3.7 EOSSources–DesignIssues 54
3.3.8 EOSFailureMechanisms 55
3.4 EMI 57
3.5 EMC 57
3.6 Latchup 58
3.7 SummaryandClosingComments 59
References 59
4 SystemLevelESD 65
4.1 SystemLevelTesting 65
4.1.1 SystemLevelTestingObjectives 66
4.1.2 DistinctionofSystemandComponentLevelTestingFailure
Criteria 66
4.2 WhenSystemsandChipsInteract 67
4.3 ESDandSystemLevelFailures 68
4.3.1 ESDCurrentandSystemLevelFailures 68
4.3.2 ESDInducedE-andH-FieldsandSystemLevelFailures 69
4.4 ElectronicSystems 70
4.4.1 CardsandBoards 70
4.4.2 SystemChassisandShielding 71
4.5 SystemLevelProblemsToday 71
4.5.1 HandHeldSystems 71
4.5.2 CellPhones 71
4.5.3 ServersandCables 72
4.5.4 LaptopsandCables 74
4.5.5 DiskDrives 74
4.5.6 DigitalCameras 75
4.6 Automobiles,ESD,EOS,andEMI 77
4.6.1 AutomobilesandESD–IgnitionSystems 77
4.6.2 AutomobilesandEMI–ElectronicPedalAssemblies 77
4.6.3 AutomobilesandGasTankFires 78
x CONTENTS
4.6.4 HybridsandElectricCars 78
4.6.5 AutomobilesintheFuture 79
4.7 AerospaceApplications 80
4.7.1 Airplanes,PartialDischarge,andLightning 80
4.7.2 Satellites,SpacecraftCharging,andSingleEventUpset(SEU) 81
4.7.3 SpaceLandingMissions 81
4.8 ESDandSystemLevelTestModels 83
4.9 IEC61000-4-2 83
4.10 HumanMetalModel(HMM) 83
4.11 ChargedBoardModel(CBM) 86
4.12 CableDischargeEvent(CDE) 87
4.12.1 CableDischargeEvent(CDE)andScaling 89
4.12.2 CableDischargeEvent(CDE)–CableMeasurementEquipment 89
4.12.3 CableConfiguration–TestConfiguration 92
4.12.4 CableConfiguration–FloatingCable 92
4.12.5 CableConfiguration–HeldCable 92
4.12.6 CableDischargeEvent(CDE)–PeakCurrentvs.ChargedVoltage 92
4.12.7 CableDischargeEvent(CDE)–PlateauCurrentvsChargedVoltage 92
4.13 SummaryandClosingComments 93
References 93
5 ComponentLevelIssues–ProblemsandSolutions 97
5.1 ESDChipProtection–TheProblemandtheCure 97
5.2 ESDChipLevelDesignSolutions–BasicsofDesignSynthesis 98
5.2.1 ESDCircuits 101
5.2.2 ESDSignalPinProtectionNetworks 101
5.2.3 ESDPowerClampProtectionNetworks 103
5.2.4 ESDPowerDomain-to-DomainCircuitry 103
5.2.5 ESDInternalSignalLineDomain-to-DomainProtectionCircuitry 104
5.3 ESDChipFloorPlanning–BasicsofDesignLayoutandSynthesis 105
5.3.1 PlacementofESDSignalPinHBMCircuitry 106
5.3.2 PlacementofESDSignalPinCDMCircuitry 107
5.3.3 PlacementofESDPowerClampCircuitry 107
5.3.4 PlacementofESDV -to-V Circuitry 109
SS SS
5.4 ESDAnalogCircuitDesign 109
5.4.1 SymmetryandCommonCentroidDesignforESDAnalogCircuits 110
5.4.2 AnalogSignalPintoPowerRailESDNetwork 111
5.4.3 CommonCentroidAnalogSignalPintoPowerRailESDNetwork 111
5.4.4 Co-synthesisofCommonCentroidAnalogCircuitand
ESDNetworks 112
5.4.5 SignalPin-to-SignalPinDifferentialPairESDNetwork 113
5.4.6 CommonCentroidSignalPinDifferentialPairESDProtection 113
5.5 ESDRadioFrequency(RF)Design 115
5.5.1 ESDRadioFrequency(RF)DesignPractices 115
5.5.2 ESDRFCircuits–SignalPinESDNetworks 121
CONTENTS xi
5.5.3 ESDRFCircuits–ESDPowerClamps 123
5.5.4 ESDRFCircuits–ESDRFVSS-to-VSSNetworks 126
5.6 SummaryandClosingComments 127
References 127
6 ESDinSystems–ProblemsandSolutions 129
6.1 ESDSystemSolutionsfromLargesttoSmallest 129
6.2 AerospaceSolutions 129
6.3 OilTankerSolutions 130
6.4 AutomobileSolutions 130
6.5 Computers–Servers 131
6.5.1 Servers–TouchPadsandHandlingProcedures 131
6.6 MotherBoardsandCards 131
6.6.1 SystemCardInsertionContacts 131
6.6.2 SystemLevelBoardDesign–GroundDesign 131
6.7 SystemLevel“OnBoard”ESDProtection 133
6.7.1 SparkGaps 134
6.7.2 FieldEmissionDevices(FED) 136
6.8 SystemLevelTransientSolutions 140
6.8.1 TransientVoltageSuppression(TVS)Devices 141
6.8.2 PolymerVoltageSuppression(PVS)Devices 143
6.9 Package-LevelMechanicalESDSolutions–Mechanical“Crowbars” 144
6.10 DiskDriveESDSolutions 145
6.10.1 InLine“ESDShunt” 145
6.10.2 Armature–Mechanical“Shunt”–ABuilt-InElectrical“Crowbar” 145
6.11 SemiconductorChipLevelSolutions–FloorPlanning,Layout,and
Architecture 147
6.11.1 MixedSignalAnalogandDigitalFloorPlanning 147
6.11.2 Bipolar-CMOS-DMOS(BCD)FloorPlanning 148
6.11.3 System-onChipDesignFloorPlanning 148
6.12 SemiconductorChipSolutions–ElectricalPowerGridDesign 149
6.12.1 HMMandIECSpecificationPowerGridandInterconnectDesign
Considerations 150
6.12.2 ESDPowerClampDesignSynthesis–IEC61000-4-2
ResponsiveESDPowerClamps 151
6.13 ESDandEMC–WhenChipsBringDownSystems 152
6.14 SystemLevelandComponentLevelESDTestingandSystem
LevelResponse 152
6.14.1 TimeDomainReflection(TDR)andImpedanceMethodologyfor
ESDTesting 152
6.14.2 TimeDomainReflectometry(TDR)ESDTestSystemEvaluation 154
6.14.3 ESDDegradationSystemLevelMethod–EyeTests 158
6.15 EMCandESDScanning 160
6.16 SummaryandClosingComments 163
References 164