Enhancement of timing accuracy and waveform quality in high performance ASIC test and ...

299 Pages·2010·10.68 MB·English

by  Boonying Charoen

ENHANCEMENT OF TIMING ACCURACY
AND WAVEFORM QUALITY
IN HIGH PERFORMANCE
ASIC TEST AND VERIFICATION
SYSTEMS
A thesis presented for the degree of
Doctor of Philosophy
.
In
Electrical and Electronic Engineering
at the
University of Canterbury,
Christchurch,
New Zealand.
by
Boonying 9haroen
B. Eng.
December 1991

ENGINEERING
LIBRARY
ABSTRACT
This thesis reviews design, test, and verification aspects of Application-Specific Inte
grated Circuits (ASIC). A means of improving edge-placement accuracy and waveform
quality in high speed, high performance, ASIC test and verification systems has been
developed. Its aim is to minimize timing skew, maintain signal integrity at the Device
Under Test (DUT), and actively reduce waveform distortions caused by uncertain DUT
loading and transmission path imperfections.
Frequency Domain Reflectometry (FDR) is used to measure voltage reflection coef
ficients of both the load (DUT) and Pin Electronic Card (PEC) ends of the transmis
sion path. Time domain waveform is obtained using Discrete Fourier Transformation
(DFT).
Two prototypes, single and dual directional couplers, have been designed and imple
mented using Thickfilm-Hybrid Technology (TFH). Both couplers employ strip trans
mission line structures which support a Transverse Electromagnetic (TEM) propagation
mode. FDR experimental results indicate that a matched dual direction.al coupler can
be used in such an application, yielding results comparable to those obtained from an
automatic network analyzer.
The path between the PEC and the DUT is modelled using a signal flow graph
(SFG) technique. The model contains both lumped, and distributed circuit elements,
each of which is represented by scattering parameters. Load models that represent
the DUT or PEC receiver are obtained through a direct search optimization algorithm.
This thesis implements two such algorithms, the pattern search and simplex algorithms,
based on an example load model.
A technique to compute compensation waveforms for linear transmission paths has
been developed. Two examples, matched and mismatched channels, are presented.
Simulation results show that compensation waveforms computed from the channel char
acteristic almost completely correct edge-placement timing errors and greatly reduce
reflection effects. Implementation of compensation waveforms by simple hardware is
possible, leading to edge-placement correction which is almost as good as that obtained
from a theoretically computed compensation waveform.

ACKNOWLEDGEMENT
I gratefully thank my supervisor, Mr. 1. N. M. Edward, for his advice, stimulation,
and constant support throughout the project. His time spent reading and editing this
thesis is very much appreciated.
I would like to acknowledge the New Zealand Government, especially the Ministry
of External Relations and Trade, for providing financial support and giving me an
opportunity to come to study in New Zealand.
Many thanks go to the following persons who have greatly assisted me: Mr. A. J.
McMaster of the University of Auckland f01' providing S-parameter measurements; Mr.
T. J. Goodman for his contribution in the initial study ofthis project; Mr. M. V. Clark
who set up the software used in the preparation of the diagrams; Mr. S. Bly of Tait
Electronics Ltd. for the use of a signal generator used in the FDR experiment; Ms. H.
A. Devereux who worked on the technical side of the fabrication of the Thickfilm pro
totypes; Mr. P. G. Lambert for helping in the mechanical part of the second prototype
packaging; Mr. R. D. E. Berry for his patience in seeking out the components used in
this project.
I wish also to thank the many staff and postgraduate students in the Department
of Electrical and Electronic Engineering, University of Canterbury, Christchurch, New
Zealand, and all the friends I have met during my stay in New Zealand for helpful
discussion, encouragement, and assistance.

CONTENTS
PREFACE xxiii
CHAPTER 1 DESIGN AND TEST OF ASIC 1
1.1 THE PROPOSAL 1
1.2 ASIC: DESIGN AND TEST 2
1.2.1 IC Design Methodologies 2
vis
1.2.2 ASIC Standard Devices 3
1.2.2.1 ASIC features 4
1.2.2.2 Tools for a testable design 4
1.2.3 Where Testing is Performed 5
1.3 INTEGRATING DESIGN AND TEST 7
1.3.1 Design for Testability 7
1.3.2 Basic Requirements for a Testable Circuit 7
1.4 TEST DEFINITIONS AND METHODOLOGIES 7
1.4.1 Definition of Test 8
1.4.2 Test Methodologies 8
1.4.2.1 The testing purpose 8
1.4.2.2 Manufacturing level 8
1.4.2.3 Test method 9
1.5 DEVICES AND THEIR PACKAGING TECHNOLOGIES 9
1.5.1 Device Technologies 9
1.5.1.1 Comparison between DUT technologies 10
1.5.1.2 IC power dissipation vs frequency 10
1.5.2 DUT Packaging Technologies 11
1.5.2.1 Requirements for ASIC packages 11
1.5.2.2 Package hierachy 12
1.5.2.3 Design for testability at board level 14
CHAPTER 2 ASIC TEST AND VERIFICATION SYSTEM 17
2.1 THE AUTOMATIC TEST SYSTEM 17
2.1.1 Evolution of IC Automatic Test Systems 17
viii CONTENTS
2.1.2 Available Test Equipment 18
2.1.3 Tester Architecture 19
2.1.4 The Test Head 19
2.1.4.1 IC testing processes 22
2.1.4.2 The elements of a test head 23
2.2 TESTING INTERFACE 24
2.2.1 DUT-Test System Interface 24
2.2.1.1 Driving the DUT 24
2.2.1.2 Sensing DUT output 25
2.3 TRANSMISSION PATH CONSIDERATIONS 26
2.3.1 Transmission Lines in High Speed Digital Systems 26
2.3.1.1 When to use transmission line analysis? 26
2.3.1.2 Parameters for high speed performance 27
2.4 TESTER SPECIFICATIONS 27
2.4.1 Test Parameters for Digital Circuit Characterization 27
2.4.1.1 Speed 28
2.4.1.2 Timing parameters 28
2.4.1.3 The level parameters 29
2.4.1.4 The pattern format 29
2.4.1.5 Memory depth 29
2.5 SUMMARY 30
CHAPTER 3 THE PROPOSED IMPROVEMENTS 33
3.1 TIMING ACCURACY IN MODERN IC TESTERS 33
3.1.1 Toward Standardization of ATE Timing Accuracy 34
3.1.2 Sources of Timing Error in VLSI Testers 34
3.1.3 Definition of overall timing accuracy 35
3.1.4 Automatic Calibration System 36
3.1.4.1 Calibration techniques 37
3.2 THE PROPOSED CALIBRATION SYSTEM 38
3.2.1 An FDR Signal Source 38
3.2.2 Complex Impedance Measurement 39
3.2.3 Transmission Path Model 39
3.2.4 Load Model Determination 39
3.2.5 The Waveform Quality 40
3.3 FREQUENCY DOMAIN OR TIME DOMAIN
REFLECTOMETRY? 40
3.3.1 Measurement Techniques 41
3.3.1.1 Time domain reflectometry 41
3.3.1.2 Frequency domain reflectometry 42
CONTENTS IX
3.4 SUMMARY 43
CHAPTER 4 FUNDAMENTAL THEORY 45
4.1 TRANSMISSION LINE GEOMETRY 45
4.1.1 Parallel Wire and Twisted Pair 45
4.1.2 Coaxial Cable 46
4.1.3 Wire Over Ground 46
4.1.4 Microstrip Line 47
4.1.5 Strip Transmission Line 47
4.2 COMPLEX IMPEDANCE MEASUREMENT 48
4.2.1 Transmission Line Theory 48
4.2.1.1 Lossless transmission line 49
4.2.2 Impedance and Reflection Coefficient Concepts 49
4.2.2.1 Input impedance along a transmission line 50
4.2.2.2 Input impedance described by reflection
coefficient 51
4.2.3 Voltage- and Power-wave Concepts 51
4.3 SIGNAL FLOW GRAPH ANALYSIS 54
4.3.1 Network Representation 55
4.3.2 Signal Flow Graph and Scattering Parameter 56
4.3.3 Construction of Signal Flow Graphs 57
4.3.4 Scattering Matrix Renormalization 58
4.4 SIGNAL FLOW GRAPH REDUCTION METHODS 59
4.4.1 Topological Method 59
4.4.2 Algebraic Method 60
4.4.3 Matrix Method 61
CHAPTER 5 DIRECTIONAL COUPLER DESIGN AND
IMPLEMENTATION 63
5.1 THEORY OF DIRECTIONAL COUPLER 63
5.1.1 Directional Electromagnetic Couplers 64
5.1.2 Parallel Coupled-Line Directional Coupler
Parameters 64
5.1.3 Steady-State Response 65
5.1.4 Transient Response 65
5.1.4.1 A rigorous method 68
5.1.4.2 A simple method 68
5.1.4.3 Ideal step pulse response 69
5.1.4.4 Ideal ramp pulse response 70
5.1.4.5 Arbitrary pulse response 71
5.1.4.6 Timing alignment using directional coupler 72
x CONTENTS
5.2 DESIGN OF THE PROTOTYPE DIRECTIONAL
COUPLER 73
5.2.1 Coupler Geometry 74
5.2.2 Coupling Factor Selection 76
5.2.3 Design Methodologies 77
5.2.3.1 The even- and odd-mode characteristic
impedances 79
5.2.3.2 Coupler line width and spacing 79
5.2.3.3 Single strip line width 82
5.2.3.4 The physical length 82
5.3 IMPLEMENTATION OF THE PROTOTYPE
DIRECTIONAL COUPLERS 83
5.3.1 Layout Generation 83
5.3.2 Artwork Generation 84
5.3.3 Photofabrication 84
5.3.4 The Screen Making and Printing Process 84
5.3.5 Substrate Drying and Firing 84
5.3.6 Resistor Trimming Process 86
5.3.7 Materials 86
5.4 THE PHYSICAL STRUCTURE 86
5.4.1 The Single Directional Coupler 87
5.4.2 The Dual Directional Coupler 89
5.5 COUPLER TEST RESULTS 89
5.5.1 Coupler Line Width and Spacing Measurement 92
5.5.2 Directional Coupler S-parameters 92
5.6 CONCLUSION 96
CHAPTER 6 THE FDR EXPERIMENT 97
6.1 OBJECTIVES 97
6.1.1 The Construction of the Terminations 97
6.2 MEASUREMENT CONFIGURATION 98
6.2.1 Relative Reflection Coefficient Measurement 99
6.2.2 The Reference Loads 102
6.2.3 Output Voltages at Ports 3 and 4 102
6.3 MEASUREMENT RESULTS 102
6.3.1 The HP778D Dual Directional Coupler Load
Measurement Results 104
6.4 DISCUSSION OF THE RESULTS 104
6.4.1 Measurement Error Sources 104
6.4.2 The Measurement Uncertainty 115