Designing VLSI Circuits and Systems with Nano Electro-Mechanical Relays

20 Pages·2011·1.08 MB·English

CMOS ET Workshop 2011
Designing VLSI Circuits and Systems
with Nano Electro-Mechanical Relays
Vladimir Stojanović (MIT)
in collaboration with
Tsu-Jae King Liu, Elad Alon (UC Berkeley)
Dejan Marković (UCLA)
June 16, 2011
Subthreshold Leakage: Game Over for CMOS
25
p p
o o 11 More parallelism
/ 20 /
y y
does not help
g g
r r
e e
10
n 15 n
E E
1x
d d
E
e e
total
z 10 z 9
i i
la la 8x 2x
E
m dynamic m
r 5 r
o o
8
N N
E
leakage
0.1 0.2 0.3 0.4 0.5 0 1 2 3 4 5 6
V (V) 1/throughput
DD
Leakage and sub-threshold slope define minimum

energy/op for CMOS
Parallelism cannot reduce power/throughput if already

operating at minimum energy
2
NEM Relays to the Rescue
Measured MEM Relay I-V Curve MEM Relay Energy vs. V
DD
E =E
total dynamic
NEM relays show zero leakage & sharp sub-threshold slope

Could potentially enable reduced E/op with scaling

E set by contact bond energy

min
~2aJ/switch (50x better than 90nm CMOS)

R. Nathanael et al., “4-Terminal Relay Technology for Complementary Logic,” IEDM 2009
3
3
NEM Relay Structure and Operation
Tungsten Body
Poly-SiGe Gate
Tungsten Channel
Poly-SiGe Anchor
Poly-SiGe Beam
/Flexure
Tungsten Source/Drain
OFF Relay:
|V | < V (pull-out voltage)
gb po
ON Relay:
|V | > V (pull-in voltage)
gb pi
4
Power-gating CMOS with NEM Relays
8
G B G
)
V 7
( V 85μm
G 2
V 6 = m
V G S μ D
D 55
5
1.2
V) 0.8 G G
(

D
D
V 0.4
V V
H EXT,R
0
V) 3 ROSC A
(

S
O 2
M
C
nc 1 R1 C1 C VG
y OSC
S
0
-0.1 -0.05 0 0.05 0.1 0.15
V
Time (s) b
R2 C2 External Power gate
pulse gen
V
DD
3% Duty Cycle Self-driven pulse generator to CMOS logic
8
6
)
V
(

e4
g
Power-gating input (V )
a OSC
t
ol
V
2
H. Fariborzi et al. Gated CMOS V
DD
CICC 2010
0
0 0.5 1 1.5 2 2.5 3 3.5
Time (s)
5
Energy Gain Over CMOS Limited to Large T
off
8
10
V V
EXT,M EXT,R
7
10
sleep V
sleep V G
IO
6
10
CM V CR VDD
DD
γC eC
105 M R
)
s

( V CMOS LOGIC CMOS LOGIC
T off 104 EEXnT,eMrgy ga,in,f,C βCL , ,f,C βCL
p L p L
1
3
10 2
(a) (b)
5
2
10 10
V =V V =V
IO NOM IO EXT,M
1
10
32 45 65 90 130 180 250
Technology node (nm)
E kR I T
Energy gGain GM  on,M off  off

E V T
Large T R DD on

off
Switching overhead negligible

6
Area Savings More Significant
2
10
1
10
90nm
0
10 CMOS Scaled
Relay
-1
10
Peak
]
2
m Current
Current m 10-2 Relay
A/ Ton overhead
[
n MOS 10s 1%
density o
I -3 MOS 1ms 1%
10
MOS 10s 10%
MOS 1ms 10%
-4
10
T R
on on,R
Relay 10s 10k
-5
10 Relay 1ms 10k
Relay 10s 1k
Relay 1ms 1k
-6
10
-2 -1 0 1 2
10 10 10 10 10
MOS technology node and relay device pitch [m]
Relays fabricated in metal backend - no area overhead

Today: 1 mA/mm2 (ready for low-power apps)

Scaled: 10-100 mA/mm2 (ready for high-power apps)

7
NEM Relay as a Logic Element
Anchor
Mechanical
Spring k Model
Damper b
Mass m
G
S Cgc D
Rs Rd
R C R
cs gb cd
C C
sb db
Simple model

B
Mechanical – spring, mass, damper

Electrical – RC

4-terminal relay mimics MOSFET switch

Electrostatic actuation is ambipolar

Non-inverting logic is possible

Actuation independent of source/drain voltages

8
Digital Circuit Design with NEM Relays
NEMS: 12 switches
CMOS: delay set by electrical time constant

Quadratic delay penalty for stacking devices

Buffer & distribute logical/electrical effort over many stages

NEMS: delay dominated by mechanical movement

Can stack ~100-200 devices before t ≈ t

d,elec d,mech
So, want all to switch simultaneously

 Implement logic as a single complex gate

9
Need to Compare at Block Level
NEMS: 12 relays
4 gate delays 1 mechanical delay
Delay Comparison vs. CMOS

Single mechanical delay vs. several electrical gate delays

For reasonable load, NEMS delay unaffected by fan-out/fan-in

Area Comparison vs. CMOS

Larger individual devices

But often need fewer devices to implement same function

F. Chen et al., “Integrated Circuit Design with NEM Relays,” ICCAD 2008
10