Table Of ContentWORKSHOPS IN COMPUTING
Series edited by C. J. van Rijsbergen
Also in this series
AI and Cognitive Science '89, Dublin City University, Eire,
14-15 September 1989
A F. Smeaton and G. McDermott (Eds.)
Specification and Verification of Concurrent Systems, University of
Stirling, Scotland, 6--8 July 1988
C. Rattray (Ed.)
Semantics for Concurrency, Proceedings of the International
BCS-FACS Workshop, Sponsored by Logic for IT (S.E.R.C.), University
of Leicester, UK, 23-25 July 1990
M. Z. Kwiatkowska, M. W. Shields and R. M. Thomas (Eds.)
Functional Programming, Proceedings of the 1989 Glasgow
Workshop, Fraserburgh, Scotland, 21-23 August 1989
K. Davis and J. Hughes (Eds.)
Persistent Object Systems, Proceedings of the Third International
Workshop, Newcastle, Australia, 1G --13 January 1989
J. Rosenberg and D. Koch (Eds.)
Z User Workshop, Proceedings of the Fourth Annual Z User Meeting,
Oxford, 15 December 1989
J. E. Nicholls (Ed.)
Formal Methods for Trustworthy Computer Systems (FM89), Halifax,
Canada, 23-27 July 1989
Dan Craigen (Editor) and Karen Summerskill (Assistant Editor)
Security and Persistence, Proceedings of the International Workshop
on Computer Architectures to Support Security and Persistence of
Information, Bremen, West Germany, 8-11 May 1990
John Rosenberg and J. Leslie Keedy (Eds.)
Women into Computing: Selected Papers 1988-1990
Gillian Lovegrove and Barbara Segal (Eds.)
3rd Refinement Workshop, Proceedings of the 3rd Refinement
Workshop (organised by BCS-FACS, and sponsored by IBM UK
Laboratories, Hursley Park and the Programming Research Group,
University of Oxford) 9--11 January 1990, Hursley Park
Carroll Morgan and J. C. P. Woodcock (Eds.)
Functional Programming, Glasgow 1990, Proceedings of the 1990
Glasgow Workshop on Functional Programming, 13-15 August 1990,
Ullapool, Scotland
Simon L. Peyton Jones, Graham Hutton and Carsten Kehler Holst
(Eds.)
Geraint Jones and Mary Sheeran (Eds.)
Designing Correct Circuits
Workshop jointly organised by the
Universities of Oxford and Glasgow
26-28 September 1990, Oxford
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Published in collaboration with the
British Computer Society
IB3<C~
Springer-Verlag London Ltd.
Geraint Jones
Oxford University Computing Laboratory
11 Keble Road
Oxford, OX1 300, England
Mary Sheeran
Department of Computing Science
University of Glasgow
Glasgow, G12 800, Scotland
ISBN 978-3-540-19659-4 ISBN 978-1-4471-3544-9 (eBook)
DOI 10.1007/978-1-4471-3544-9
British Library Cataloguing in Publication Data
Designing correct circuits
1 . Computers. Circuits
1. Jones, Geraint 1957- 11. Sheeran, Mary 1959- III. British Computer
Society IV. Series
621.395
C.I.P. Data available
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© Springer-Verlag London 1991
Originally published by British Computer Society in 1991.
The use of registered names, trademarks etc. in this publication does not
imply, even in the absence of a specific statement, that such names are
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34/383(}-54321 O Printed on acid-free paper
Preface
These proceedings contain the papers presented at a workshop on
Designing Correct Circuits, jointly organised by the Universities of
Oxford and Glasgow, and held in Oxford on 26-28 September 1990.
There is a growing interest in the application to hardware design of the
techniques of software engineering. As the complexity of hardware
systems grows, and as the cost both in money and time of making
design errors becomes more apparent, so there is an eagerness to
build on the success of mathematical techniques in program develop
ment. The harsher constraints on hardware designers mean both that
there is a greater need for good abstractions and rigorous assurances
of the trustworthyness of designs, and also that there is greater reason
to expect that these benefits can be realised. The papers presented at
this workshop consider the application of mathematics to hardware
design at several different levels of abstraction.
At the lowest level of this spectrum, Zhou and Hoare show how to
describe and reason about synchronous switching circuits using
UNilY, a formalism that was developed for reasoning about parallel
programs. Aagaard and Leeser use standard mathematical tech
niques to prove correct their implementation of an algorithm for
Boolean simplification. The circuits generated by their formal synthesis
system are thus correct by construction. Thuau and Pilaud show how
the declarative language LUSTRE, which was designed for program
ming real-time systems, can be used to specify synchronous circuits.
They also present a tool for the automatic verification of circuit
correctness. Collavizza and Borrione also use a functional formalism:
they specify the micro-program parallelism of von Neumann style
microprocessors. Luk shows how to optimise array-based designs by
systematically rearranging components and interconnections.
Delgado Kloos and Dosch show that it is possible to derive both
asynchronous and synchronous implementations from a single speci
fication. Zhu and Johnson consider data abstraction in an algebraic
framework, and by now we are almost at the other extreme of the
spectrum.
The topical area of the design of delay-insensitive circuits is repre
sented by two papers. Josephs and Udding present an algebra in which
vi Preface
expressions specify delay-insensitive circuits; they illustrate their
method by designing a delay-insensitive stack. Brown shows how to
compile programs written in a subset of occam* into delay-insensitive
circuits. He demonstrates that it is possible to build interesting and
purely delay-insensitive circuits using only a small set of building blocks.
Akella and Gopalakrishnan also use a process algebra to describe
hardware: they consider the problem of high-level test generation.
The idea of building a logic for hardware design on top of a theorem
prover is also a hot topic in the field. Mendler builds a logic for design
with constraints using the LEGO theorem prover. The Isabelle theorem
prover provides the basis for Suk's constructive type theory for
hardware synthesis and for Rossen's implementation of the algebra of
the relational hardware design language Ruby. Busch shows how to do
correctness-preserving circuit transformations using the LAMBDA
system. Camurati, Margaria and Prinetto report on their experiences in
using a First Order Logic theorem prover (OTTER) to verify the
correctness of combinational logic. Joyce advocates the use of generic,
that is parametrised, specifications and shows how they fit well in the
context of Higher Order Logic (HOL). His paper also provides a good
introduction to formal verification using the HOL system. Eker,
Stavridou and Tucker use OBJ3 as a theorem proving tool for the
verification of synchronous concurrent algorithms.
The papers present a good cross section of current work developing
and applying formal methods in circuit design.
The papers in this volume were refereed before being selected for
presentation, and have been revised in the light of the discussion at the
workshop. We would like to thank the following referees and members
of the program committee: Raymond Boute, Shiu-Kai Chin, John
O'Donnell, Mike Fourman, Damir Jamsek, Steve Johnson, Wayne Luk,
Tom Melham, Christian D. Nielsen, Donna E. Peterson, Jan van de
Snepscheut, Edward P. Stabler, and J0rgen Staunstrup.
5th November 19 90 Geraint Jones
Mary Sheeran
*occarr is a trade mark of INMOS Umited
Contents
Constrained Proofs: A Logic for Dealing with Behavioural
Constraints in Formal Hardware Verification
Michael Mendler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Hardware Synthesis in Constructive Type Theory
DanySuk ..................................................................................... 29
An Algebraic Framework for Data Abstraction in Hardware
Description
Zheng Zhu and Steven D. Johnson .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 50
Generic Specification of Digital Hardware
Jeffrey J. Joyce . .. . . . . . . . . .. . . .. .. .. .. . . . . . . . . .. . . . . . . . . . . . . .. . . .. .. . . . . . . .. . . . . . . .. . .. . . . . 68
Sampling and Proof: A Half-case Study (Invited evening lecture)
John Hughes . .. . . . . .. .. . . . . . . . . . . . . . . . . .. . . . . . . . . .. .. .. .. . . . . . . . . . .. . . . .. . . . . .. .. .. . . . . . . .. 92
High Level Test Generation via Process Composition
Venkatesh Akella and Ganesh Gopalakrishnan .. .. .. .. .. .. .. .. .. .. .. .. .. .. 99
Towards Truly Delay-insensitive Circuit Realizations of Process
Algebras
Geoffrey M. Brown ....................................................................... 120
The Design of a Delay-insensitive Stack
Mark B. Josephs and Jan Tijmen Udding .................................... 132
Specifying the Micro-program Parallelism for Microprocessors
of the von Neumann Style
Helene Collavizza and Dominique Borrione .................................. 153
The Implementation and Proof of a Boolean Simplification System
Mark Aagaard and Miriam Leeser ................................................ 171
A Model for Synchronous Switching Circuits and its Theory of
Correctness
Zhou Chaochen and C. A. R. Hoare ............................................ 196
Efficient Circuits as Implementations of Non-strict Functions
Carlos Delgado Kloos and Walter Dosch ..................................... 212
viii Contents
Verification of Synchronous Concurrent Algorithms using OBJ3:
A Case Study of the Pixel-planes Architecture
S. M. Eker, V. Stavridou and J. V. Tucker .................................... 231
Use of the OTIER Theorem Prover for the Formal Verification of
Hardware
Paolo Camurati, Tiziana Margaria and Paolo Prinetto ................... 253
Proof-based Transformation of Formal Hardware Models
Holger Busch ............................................................................... 271
Ruby Algebra
Lars Rossen ................................................................................. 297
Using the Declarative Language LUSTRE for Circuit Verification
Ghislaine Thuau and Daniel Pilaud ............................................... 313
Optimising Designs by Transposition
Wayne Luk ................................................................................... 332
Author Index ................................................................................ 355
Constrained Proofs:
A Logic for Dealing with Behavioural Constraints
1n Formal Hardware Verification*
Michael Mendlert
Department of Computer Science
University of Edinburgh
Abstract
The application of formal methods to the design of correct computer hardware de
pends crucially on the use of abstraction mechanisms to partition the synthesis and
verification task into tractable pieces. Unfortunately however, behavioural abstractions
are genuine mathematical abstractions only up to behavioural constraints, i.e. under
certain restrictions imposed on the device's environment. Timing constraints on input
signals form an important class of such restrictions. Hardware components that behave
properly only under such constraints satisfy their abstract specifications only approxi
mately.
This is an impediment to the naive approach to formal verification since the question
of how to apply a theorem prover when one only knows approximately what formula to
prove has not as yet been dealt with.
In this paper we propose a notion of constrained proof and constrained proposition
which provides for 'approximate' verification of abstract specifications and yet does
not compromise the rigour of the argument. It is based on the idea of removing the
constraints from the specification and making them part of its proof. Thereby the
abstract verification is separated from constraint analysis which in turn may be delayed
arbitrarily. We have implemented the logic on the interactive theorem prover LEGO
and verified simple examples. The presentation in this paper uses one of these examples
for explaining the problem and demonstrating the use of the logic.
•This work was supported by tbe Studienstiftung des deutschen Volkes and SERC grant No.GR/F 35890
"Formal System Design"
fNow at University of Erlangen-Niirnberg, Institute for Computer Aided Circuit Design, email
[email protected]. de or mm @lfcs.ed.ac. uk
