Designing 2D and 3D Network-on-Chip Architectures

271 Pages·2014·7.291 MB·English

by  Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch (auth.)

Konstantinos Tatas · Kostas Siozios
Dimitrios Soudris · Axel Jantsch
Designing 2D and
3D Network-on-
Chip Architectures
Designing 2D and 3D Network-on-Chip
Architectures
Konstantinos Tatas Kostas Siozios
•
Dimitrios Soudris Axel Jantsch
•
Designing 2D and 3D
Network-on-Chip
Architectures
123
Konstantinos Tatas Axel Jantsch
Department of Computer Science Department of ElectronicSystems
and Engineering, Schoolof Royal InstituteofTechnology
AppliedSciences Kista
Frederick University Sweden
Nicosia
Cyprus
Kostas Siozios
Dimitrios Soudris
Department of Computer Science,School
of Electricaland Computer Engineering
National Technical Universityof Athens
Athens
Greece
ISBN 978-1-4614-4273-8 ISBN 978-1-4614-4274-5 (eBook)
DOI 10.1007/978-1-4614-4274-5
SpringerNewYorkHeidelbergDordrechtLondon
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(cid:2)SpringerScience+BusinessMediaNewYork2014
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Preface
Moore’s law continues unabated and new design challenges lead to new design
methodologies and even paradigm shifts. One such recent development is the
introduction of three-dimensional integration technology. Efficiently utilizing
novel technologies poses new design challenges and therefore require new design
methodologies and EDA tools. Training engineers in these methodologies and
design techniques is essentially done at the graduate level and once these tech-
nologies become the established paradigm, at the undergraduate level.
Network-on-Chip technology has been a popular research topic for a while
now,andisthecurrentdesignparadigmformulti-andmany-corearchitectures.It
is also a natural complement for 3D integration technology. Its multifaceted and
multidisciplinarynatureimposesanumberofchallengesbothintheindustrialand
academic environments. While at the graduate level it is common or even pref-
erabletousepapers,casestudiesandassignmentsasthemainteachingtools,atthe
undergraduate level a suitable textbook is indispensable. Since there is an
increased need to include an introduction to Networks-on-Chip in undergraduate
curricula,suchatextbookisrequired,andhasbeenmissingfromtheliteraturefor
too long. At the same time, the large body of research work in the field must be
also made available in an organized way for graduate students, researchers, and
professionals to use as reference.
Therefore, the purpose of this book is two-fold. First, to be used as an under-
graduate or graduate level textbook for introduction to Network-on-Chip tech-
nology providing students and practising engineers with the fundamentals as well
asdetailsinthemanyfacetsofNetwork-on-Chipdesign,includingrecentworkon
3D NoCs. Second, to be used as reference for researchers in the field.
For this purpose, each of the first seven chapters in the first part of the book
beginswiththeintroductionofthefundamentalconceptsassumingonlylittleprior
knowledge of the reader in the field of digital design, computer architecture, and
VLSI design. Instead, relative information is often summarized here in order to
make each chapter as self-contained as possible. At the same time, after the
introduction to the fundamentals, following advances in the area are summarized
in a survey manner with appropriate references, so that the student can immedi-
ately build upon the fundamentals while the practising researcher can easily find
relative information. Furthermore, each chapter contains a number of questions,
problems, and design assignments that can be used in the class or the laboratory.
v
vi Preface
These first seven chapters can be used as an introductory course in NoC design
either at the undergraduate or graduate level.
Thenextfourchaptersinthefirstpartofthebookcontaincasestudiesfromthe
academia and industry, which can be used as a second (graduate-level) course in
NoC design.
The second part of the book contains proposed design projects covering all
aspects of NoC design, starting with design space exploration and high-level
simulation, down to the VLSI design of NoC components.
The authors would like to thank all the people who helped to make this book
possible, by contributing, providing reviews, and experimental results.
Nicosia, June 2013 Konstantinos Tatas
Athens Kostas Siozios
Athens Dimitrios Soudris
Stockholm Axel Jantsch
Contents
Part I Network-on-Chip Design Methodology
1 Network-on-Chip Technology: A Paradigm Shift. . . . . . . . . . . . . 3
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Network-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 OSI Layer Roles in a NoC . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 Application Layer. . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.2 Presentation Layer . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.3 Session Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.4 Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.5 Network Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.6 Data Link Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.7 Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Benefits and Challenges of Adopting NoCs. . . . . . . . . . . . . . 13
1.4.1 IP Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.3 Physical Constraints and Timing Closure. . . . . . . . . . 14
1.4.4 Software Observability and Security. . . . . . . . . . . . . 14
1.4.5 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4.6 EDA Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Research on On-Chip Networks. . . . . . . . . . . . . . . . . . . . . . 15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 NoC Modeling and Topology Exploration . . . . . . . . . . . . . . . . . . 19
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Topology Exploration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.1 Regular Versus Irregular Topologies. . . . . . . . . . . . . 20
2.2.2 Direct Versus Indirect Topologies . . . . . . . . . . . . . . 21
2.2.3 2-D NoC Topologies. . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.4 3-D Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Traffic Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.1 Available Models for Traffic. . . . . . . . . . . . . . . . . . 31
2.3.2 Synthetic Traffic: Temporal Distribution. . . . . . . . . . 32
vii
viii Contents
2.3.3 Synthetic Traffic: Spatial Distribution. . . . . . . . . . . . 33
2.3.4 Realistic Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4 Topology Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.1 Modeling Environment . . . . . . . . . . . . . . . . . . . . . . 36
2.4.2 Different Abstraction Levels for Noc Modeling . . . . . 38
2.5 Topology Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Application Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7 Benchmarking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8 Exercises. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3 Communication Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.1 Switching Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.1.1 Circuit Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.1.2 Packet Switching . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.1.3 Hybrid Switching Techniques . . . . . . . . . . . . . . . . . 57
3.2 Packet Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.1 Deadlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.2 Livelock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2.3 Routing Algorithms for Regular Architectures. . . . . . 61
3.2.4 Routing Algorithms for Irregular Architectures . . . . . 64
3.2.5 Topology-Agnostic Routing Algorithms . . . . . . . . . . 65
3.2.6 Bufferless Routing Algorithms. . . . . . . . . . . . . . . . . 66
3.2.7 Routing Algorithm Comparison . . . . . . . . . . . . . . . . 67
3.3 QoS, Congestion Control and Flow Control. . . . . . . . . . . . . . 67
3.3.1 Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.2 Quality of Service (QoS). . . . . . . . . . . . . . . . . . . . . 70
3.4 Router Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.4.1 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.4.2 Switch Fabric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.4.3 Port Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.4.4 Bufferless Router Design. . . . . . . . . . . . . . . . . . . . . 79
3.4.5 3-D NoC Router Design . . . . . . . . . . . . . . . . . . . . . 80
3.4.6 Router Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.5 Network Link Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.5.1 Planar Link Design. . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.2 Vertical Link Design. . . . . . . . . . . . . . . . . . . . . . . . 87
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4 Power and Thermal Effects and Management . . . . . . . . . . . . . . . 97
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.1 Models for Power, Energy, and Temperature. . . . . . . 100
4.1.2 Wear-Out Mechanisms . . . . . . . . . . . . . . . . . . . . . . 101
Contents ix
4.2 Classification of Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 Fault Tolerant Systems . . . . . . . . . . . . . . . . . . . . . . 105
4.3 Fault Tolerance Metrics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.1 Countermeasures For a Fault-Tolerant System. . . . . . 107
4.3.2 Fault Tolerance at Different Layer of Abstractions. . . 108
4.4 Error Control Coding for On-Chip Signaling. . . . . . . . . . . . . 112
4.4.1 Linear Block Codes . . . . . . . . . . . . . . . . . . . . . . . . 113
4.4.2 Hamming Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.4.3 Cyclic Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.4.4 BCH Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.4.5 Reed-Solomon Codes . . . . . . . . . . . . . . . . . . . . . . . 116
4.5 Power and Energy Savings in NOCs. . . . . . . . . . . . . . . . . . . 117
4.5.1 Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.5.2 Data-Link Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.5.3 Network Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.4 Transport Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.6 On Designing Reliable NoCs. . . . . . . . . . . . . . . . . . . . . . . . 120
4.6.1 Reliability Improvement Through
Mapping Algorithms. . . . . . . . . . . . . . . . . . . . . . . . 120
4.6.2 Reliability Improvement Through
Routing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 121
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5 NoC-Based System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.1 NoC Interface Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.1.1 Message, Packet and Flit Format . . . . . . . . . . . . . . . 128
5.1.2 Basic Network Interface Design. . . . . . . . . . . . . . . . 130
5.1.3 Advanced Network Interface Features. . . . . . . . . . . . 136
5.2 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2.1 Globally Asynchronous Locally
Synchronous (GALS) . . . . . . . . . . . . . . . . . . . . . . . 139
5.2.2 Mesochronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.2.3 Multisynchronous. . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.2.4 Asynchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.3 NoC-Based System Floorplanning . . . . . . . . . . . . . . . . . . . . 141
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6 NoC Verification and Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.2 NoC Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.2.1 Verification Fundamentals. . . . . . . . . . . . . . . . . . . . 148
6.2.2 Verification Plan . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.2.3 Test-Bench Creation for NoC. . . . . . . . . . . . . . . . . . 151
6.2.4 NoC Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 152
x Contents
6.3 Testing Fundamentals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.1 2-D IC Defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.2 3-D IC Defects. . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
6.3.3 Fault Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.3.4 Design for Testability. . . . . . . . . . . . . . . . . . . . . . . 155
6.4 NoC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.4.1 BIST Structures for NoC. . . . . . . . . . . . . . . . . . . . . 156
6.4.2 NoC as Test Access Mechanism. . . . . . . . . . . . . . . . 157
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7 The Spidergon STNoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.2 Spidergon STNoC Architecture . . . . . . . . . . . . . . . . . . . . . . 162
7.3 The Spidergon STNoC Topology. . . . . . . . . . . . . . . . . . . . . 164
7.3.1 Theoretical Foundations . . . . . . . . . . . . . . . . . . . . . 166
7.3.2 Open Source System-Level Simulation
in Spidergon STNoC. . . . . . . . . . . . . . . . . . . . . . . . 170
7.3.3 Custom Tools for Design Space Exploration . . . . . . . 171
7.3.4 Related Open Tools for NoC Design
Space Exploration. . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.4 The Spidergon STNoC Routing Algorithm . . . . . . . . . . . . . . 176
7.4.1 Across-First Routing. . . . . . . . . . . . . . . . . . . . . . . . 177
7.4.2 Across-First Zero VC Routing. . . . . . . . . . . . . . . . . 180
7.4.3 Across-Last Routing. . . . . . . . . . . . . . . . . . . . . . . . 181
7.4.4 Across-Last Zero VC Routing . . . . . . . . . . . . . . . . . 182
7.5 Fault Tolerant Routing on Spidergon STNoC. . . . . . . . . . . . . 183
7.5.1 NoC Reconfigurability Using Meta-NoC. . . . . . . . . . 186
7.6 Conclusion and Future Extensions . . . . . . . . . . . . . . . . . . . . 188
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
8 Middleware Memory Management in NoC . . . . . . . . . . . . . . . . . 191
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8.2 Categorization of Dynamic Memory Managers. . . . . . . . . . . . 192
8.3 NoC Platform Example Providing Middleware Services . . . . . 194
8.3.1 Microcoded DMM on NoC Platform. . . . . . . . . . . . . 195
8.3.2 Evaluation of Microcoded DMM . . . . . . . . . . . . . . . 201
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
9 On Designing 3-D Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
9.1 3-D Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
9.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.3 Employed Framework for Quantifying 3-D Chips. . . . . . . . . . .
9.4 Pre-processing Step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
9.5 3-D Stack Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213