Correcting Two Deletions and Insertions in Racetrack Memory

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by  Alireza Vahid

Correcting Two Deletions and Insertions in
Racetrack Memory
Alireza Vahid, Georgios Mappouras, Daniel J. Sorin, Robert Calderbank
Department of Electrical and Computer Engineering
Duke University
Abstract—Racetrack memory is a non-volatile memory engi- at least two extra reads and one extra write to access a stored
neered to provide both high density and low latency, that is bit. When an error is detected, it is corrected by reversing the
subjecttosynchronizationorshifterrors.Thispaperdescribesa
current injection and reading the memory again. The extra
fastcodingsolution,inwhich“delimiterbits”assistinidentifying
7 read/write operations and the need for additional hardware
the type of shift error, and easily implementable graph-based
1
codes are used to correct the error, once identified. A code that limittheattractivenessofthissolutionanddiminishtheappeal
0
is able to detect and correct double shift errors is described in of racetrack memory.
2
detail. We propose an alternative solution, based on codes that
n Index Terms—Racetrack memory, synchronization error, shift
detect and correct shift errors. The codes are easy to imple-
a error, insertion/deletion channel, shift error correcting codes.
J ment, and the circuits for encoding and decoding consume
3 little power. Our coding solution does not require additional
I. INTRODUCTION
2 hardware, and it does not introduce additional reads or writes
Historically, improvements in memory and storage have to memory.

] been due to advances in the memory technologies themselves Section IV describes a product code that can detect and
T
together with innovations by computer architects who design correct up to two shift errors every m + 3 shift operations
I
. memory and storage systems, and by coding theorists who in racetrack memory. The product structure makes it possible
s
c design codes for storing data. to decouple error detection from error correction, so that in
[
Racetrack memory is a non-volatile memory engineered the common case of no shift error, the access to stored data is

1 to provide both high density and low latency, and aims to fast.WedetectuptotwoshifterrorsbycombiningVarshamov-
v replace conventional memories such as DRAM and Flash. Tenengolts (VT) codes [13] with blocks of delimiter bits. Our
8 Racetrack memory stores data in “tape-like” tracks, and to productconstructionextendstheutilityofVTcodes,whichare
7
read a stored bit, an electric current is injected to place the limited to correcting single shift errors, and we also provide a
4
6 desiredbitundertheread-writeport.Competingtechnologies, low complexity construction for these codes. The inner code
0 such as phase-change memory (PCM) and magneto-resistive detects up to two shift errors within a single track, and is able
. random-accessmemory(MRAM)cannotmatchthedensityof tocorrectone.Theoutercodeconnectsdatastoredondifferent
1
0 racetrack memory. In terms of latency, only SRAM (which is tracks, and makes it possible to correct two shift errors.
7 a volatile technology) has a slight advantage, but it comes at
1 the cost of lower density [1]–[3]. II. RACETRACKMEMORY
:
v Racetrack uses current injection to shift magnetic domains Inthissectionweintroduceracetrackmemoryandourerror
i that store data bits on these tracks. In this technology, a dele- model.
X
tion occurs when the injected current is larger than expected
r A. Racetrack Background
causing one or more domains to be skipped. A repetition
a
occurs when the injected current is smaller than expected, Racetrack memory stores data in r parallel tape-like tracks.
so that the domain under the port does not change, and we Each data bit is stored in a magnetic domain and neighboring
read the same bit two or more times. We refer to deletion and domains are separated by a domain wall as depicted in Fig. 1.
repetitionerrorsasshifterrors.Thesetypesofsynchronization All read/write ports and the physical substrate are fixed in
error define a channel that has been studied extensively by position, and as current is passed through the track, the
informationtheorists[4]–[10].Thereisnoclosedformexpres- domainspassbymagneticread/writeportspositionednearthe
sion for the capacity of this insertion/repetition and deletion wire.
channel, but standard linear codes are known to be far from Racetrack memory suffers from deletion and repetition
optimal. For example, the rate penalty for correcting a single errors.Bitsarestoredonatrackandareaccessedbyinjecting
shift error is logarithmic in the block length, but the optimal a current to shift them and place them under the read/write
linear code has rate 1/2 [11]. port. A shift is therefore the injection of the current in order
There is some prior work in the computer architecture to place the next bit under the read/write port. If the injected
literature that seeks to handle shift errors by introducing extra current is larger than expected, then we might skip one or
read/write ports. The HiFi scheme presented in [12] requires multiplemagneticdomainsresultingindeletionerrors.Onthe
error-free under the assumptions of Section II-B, we say a
read/write
zero-error rate of k/m is achievable.
port
Theorem 1. For racetrack memory with the error model
definedinSectionIIandwithrparalleltracks,wecanachieve
a zero-error rate of
domain magnetic r−1 2(cid:96)−(cid:96)−1
wall domain R0((cid:96),r)= r × 2(cid:96)+6 , (cid:96)∈Z+, (1)
where k =2(cid:96)−(cid:96)−1 is the number of input data bits that are
Fig.1. Asingletrackwithoneread/writeport.Onebitisstoredperdomain
mapped to m=2(cid:96)+6 magnetic domains on the memory.
andtwoneighboringdomainsareseparatedbyadomainwall.
Ourcodehasthreemaincomponentsintwodimension.First
dimension is within a single track where we use Varshamov-
otherhand,iftheinjectedcurrentissmallerthanexpected,the
Tenengoltscodestostoredata.Thesecodesareabletocorrect
port’s position might not change and we might read the same
single shift errors. However, Varshamov-Tenengolts codes are
bit twice. We refer to this error as a repetition error. We refer
not capable of detecting or correcting two shift errors. We
to deletion and repetition errors as “shift errors.”
enhance these codes by appending some helper bits that
In deletion channels as studied in information theory, the
we refer to as delimiter bits which allow for double-shift-
size of the output is equal to the size of the input minus
error detection per track. The role of the delimiter bits is to
the number of deletions. However, in racetrack memory, the
convert racetrack to a traditional deletion/insertion channel.
memory controller is always going to provide the desired
The second dimension is across the r tracks where we deploy
number of bits, say n, regardless of whether an error occurs,
a single parity-check code to correct double shift errors. The
so that an error determines which n bits are provided. This
challenging part is to detect two shift errors and correct one.
is an important characteristic of racetrack memory, and a
We use a simple outer code to correct two shift errors.
consequence is that we first need to determine whether an
TherestofthepaperisdedicatedtotheproofofTheorem1.
error has occurred.
We also note that R ((cid:96),r)→1 as (cid:96),r →∞. As an example,
0
There is a difference between a repetition and an insertion.
consider (cid:96) = 6 (i.e. 57 input data bits) and r = 8. Then, we
Aninsertionmeansintroducinganewbitinastringregardless
have R (6,8)=0.7125.
0
of the value of its preceding bits. However, a repetition
requires the new bit to be equal to the bit right before it. IV. PROOFOFTHEOREM1:PRACTICALCODESFOR
Thus, a repetition error is an instance of an insertion error. RACETRACKMEMORY
Our goal is to devise a practical code thatwould allow reli- Inthissection,weintroduceourcodeforracetrackmemory
able data recovery in the presence of shift errors in racetrack and we prove Theorem 1. We start with a single track and
memory, and for that we need to define the error model. we devise a code that can correct a single shift error and
detectuptotwoshifterrorseverym+3shifts.Wethenshow
B. Error Model
how to correct two shift errors using an outer code that takes
We make the following assumptions: advantage of the spatial diversity in racetrack memory.
1) In each track and in every m+3 shifts (shift is defined On a single track, we encode the data bits into an ex-
above), at most two shift errors may occur. tended codeword of length m which consists of a Varshamov-
2) Whenreadingr paralleltracks,ineverym+3shifts(per Tenengoltscode(definedbelow)oflengthn=m−6followed
track), at most one track may have two shift errors. by six helper bits that we refer to as delimiter bits.
As we see later, if the second assumption is violated, then
Definition 2. The Varshamov-Tenengolts code VT (n) is the
we can detect the errors but we will only be able to correctly
set of all binary strings (c ,c ,...,c ) satisfying
1 2 n
decode the data on the tracks that have a single shift error.
n
A more restrictive model for deletion and insertion channels (cid:88) mod n+1
ic ≡ 0, (2)
with segmented errors was used in [14] in which only one i
i=1
shift error could happen per segment (a segment is a fixed
where the sum is evaluated as an ordinary rational integer1.
numberofinputbits).Moreoverin[14],authorsassumeeither
deletion errors or insertion errors but not a mixture of the two Remark 1. VT codes were introduced in [13] to correct
may occur in the channel; we impose no such constraint. errors on a Z-channel. It follows from (2) that these codes
are nonlinear over the binary field.
III. MAINRESULT
In this section, we present our main contribution. First, we Encoding: It is possible to construct VT (n) codes for any
need the following definition. n, but to maximize the speed of encoding and decoding
Definition 1. If any k input data bits can be mapped to some 1Technicallyspeaking,ourdefinitionisaspecificinstanceofVTcodes.In
m-bit codeword such that the k data bits can be recovered general,VTcodessatisfy(cid:80)ni=1icimod≡n+1a,andweuseda=0.
Observation
Decision
position position position position position position Checksum
m−5 m−4 m−3 m−2 m−1 m mod n+1
1 1 0 0 X X =0 noerror
1 1 0 0 X X (cid:54)=0 1del.and1rep.:erasure
1 0 0 0 X X X 1deletionerror
X 1 1 0 0 X X 1repetitionerror
0 0 0 0 X X X 2deletionerrors:erasure
X X 1 1 0 0 X 2repetitionerrors:erasure
TABLEI
RESULTINGOBSERVATIONSINPOSITIONSm−2,m−1ANDmFORALLPOSSIBLEERRORCOMBINATIONSANDXINDICATESANIRRELEVANTENTRY.
we choose n = 2(cid:96) and k = n − (cid:96) − 1, because when we need
n + 1 = 2(cid:96) + 1 the necessary modular arithmetic can be
D (x)∩D (y)=∅. (3)
executed more efficiently (see [15]). The encoding algorithm −1 −1
is described below.
The following lemma shows that VT codes are single-
deletion-error correcting codes.
1) Start with a zero-vector c of length n=2(cid:96).
Lemma1([16],[17]). Anytwobinarystringsx,y∈VT (n),
2) Set positions that are not powers of two to data bits
satisfy (3).
(there are k =n−(cid:96)−1 such positions).
3) Set s to be the minimum value that needs to be added For completeness, we present the proof of Lemma 1 in
tothechecksum(cid:80)ni=1ici tomakeitequalto0modulo Appendix A.
n+1.
Step 2: VT codes are single-insertion-error correcting
4) Set the (cid:96)+1 positions that are powers of two to the
codes. Note that a single-insertion-error correcting code is
binaryexpansion(oflength(cid:96)+1)ofs.Startfromc and
1 a single-repetition-error correcting code as well. Similar to
set it to the least significant bit of the binary expansion
what we described above, let D (x) denote the set of all
of s, and move all the way to c and set it to the most +1
n the binary strings of length n+1 that result from a single
significant bit of the binary expansion of s.
insertion in x. We have the following result that shows the
Varshamov-Tenengolts codes can be used for single-insertion-
It is straightforward to verify that the resulting codeword error-correction as well as single-deletion-error-correction.
satisfies (2). We know that in step 3 we have 0 ≤ s ≤ n.
Lemma 2. If for two binary strings of length n condition (3)
Since n=2(cid:96), the binary expansion of s is at most (cid:96)+1 bits
is satisfied, then we have
long.
D (x)∩D (y)=∅. (4)
After encoding the k data bits into a codeword c of size n, +1 +1
we append six delimiter bits to create the extended codeword
In other words, a single-deletion-error correcting code is a
of length m = n+6 that we write to the memory. The six
single-insertion-error correcting code.
delimiter bits are fixed and equal to 110000.
Proof: Suppose two binary strings x and y of length n
In the remainder of this section, we show that the extended
satisfy (3) but not (4). Suppose inserting x(cid:48) in position i of
codeword introduced above can correct a single shift error
x and y(cid:48) in position j of y results in the same sequence of
and detect up to two shift errors every m+3 shifts. Then,
lengthn+1.Withoutlossofgenerality,weassumei≤j.This
we show how we can correct two shift errors. We present our
implies that deleting x and y from x and y respectively,
j−1 i
argument in five steps. In steps 1 and 2, we show that VT
would result in the same sequence of length n − 1. This
codes are capable of correcting a single shift error. Step 3
contradicts (3), thus proving the lemma.
shows how we can detect up to two shift errors and takes into
Step 3: Our extended codeword can detect up to two
account the fact that the memory controller is always going
shift errors. In this step, we show that using the six delimiter
to provide the desired number of bits, regardless of whether
bits and the checksum condition of (2), we can detect up to
an error occurs. Step 4 show how to correct a single shift
two shift errors. Consider m consecutive magnetic domains
errorusingourextendedcodeword.Finally,step5incorporates
in racetrack memory. If no error happens, we need m − 1
spatial diversity to correct two shift errors.
shifts to access and read the m bits stored in these m
Step 1: VT codes are single-deletion-error correcting domains.Wesummarizetheresultingobservationsinpositions
codes. Consider two binary strings x = x ,x ,...,x and m−5,m−4,...,m for all possible error combinations in
1 2 n
y = y ,y ,...,y . Let D (x) and D (y) denote the set Table I. In Appendix B, we explain how Table I is obtained.
1 2 n −1 −1
ofallthebinarystringsoflengthn−1thatresultfromasingle The most interesting case is when a combination of a
deletion in x and y respectively. If we wish to use these two deletion error and a repetition error takes place prior to the
strings to store different values in a single-deletion channel, delimiter bits. In this case, we observe the delimiter bits as
track #1 1) Suppose a codeword c=(c ,c ,...,c ) from VT (n)
1 2 n
is stored in racetrack memory, and we detect a single
m magnetic deletion, and we observe c(cid:48) =(cid:0)c(cid:48),c(cid:48),...,c(cid:48) (cid:1).
data bits VT Encoder 1 2 n−1
domains 2) Setω tobetheHammingweight(numberof1’s)ofc(cid:48).
3) Calculate the checksum (cid:80)n−1ic(cid:48) and set s to be
track #2 i=1 i
the minimum amount that needs to be added to the
checksum in order to make it 0 mod n+1.
m magnetic
data bits VT Encoder 4) If s ≤ ω, we restore the codeword by adding a 0 im-
domains
mediately to the left of the rightmost s 1’s. Otherwise,
we restore the codeword by adding a 1 immediately to
the right of the leftmost (s−ω−1) 0’s.
track #r
m magnetic
Using this algorithm, we reconstruct the correct codeword
bitwise XOR VT Encoder
domains
and recover the dataword as discussed for the error free case.
Notethatwhilethedecodingalgorithmcorrectsthecodeword,
Fig. 2. Using an outer code on top of the code presented in Section IV it does not reveal where the deletion occurred.
allowsustocorrecttwoshifterrors. Correcting an insertion error: From Lemma 2, we know
that VT codes can correct an insertion. The corresponding
theerror-freecase,i.e.110000.Todetectsucherrors,wehave
Insertion Correction Algorithm is a modified version of the
the following result for VT codes.
DeletionCorrectionAlgorithmpresentedaboveandisomitted
Lemma 3. For any two binary strings x,y ∈ VT (n), y here due to space limitations.
cannot be obtained from x by a deletion followed by an
Step 5: The outer code corrects two shift errors. Suppose
insertion (or by an insertion followed by a deletion).
we detect two shift errors and the data is erased as in Table I.
Proof: Suppose x(cid:48) ∈ D (x) and y(cid:48) ∈ D (y). If y We can use an outer code to recover data in this case as
−1 −1
canbeobtainedfromxbyadeletionfollowedbyaninsertion, illustrated in Fig. 2 where the outer code is a simple single
then parity code. We note that per track we can correct single shift
errors and detect up to two shift errors.
D (x(cid:48))∩D (y(cid:48))(cid:54)=∅. (5)
+1 +1
APPENDIXA
In other words, x(cid:48) and x(cid:48) do not satisfy (4) which in turn PROOFOFLEMMA1
implies that x and y do not satisfy (3). However, this contra-
In this appendix, we prove Lemma 1. To prove the result,
dictsLemma1.Thiscontradictionprovestheresult.Asimilar
it suffices to show that after a single deletion, Varshamov-
argument can be used when an insertion is followed by a
Tenengolts codes cannot be confused and unique recovery is
deletion.
guaranteed. We borrow from the argument given in [18].
Lemma 3 immediately results in the following observation.
Suppose a codeword c = (c ,c ,...,c ) from VT (n) is
1 2 n
Corollary 1. A combination of a deletion error and an stored in Racetrack memory; and bit x ∈ {0,1} in position
insertion error on x ∈ VT (n) either results in x or in 1 ≤ p ≤ n is deleted to observe c(cid:48) = (cid:0)c(cid:48),c(cid:48),...,c(cid:48) (cid:1). Let
1 2 n−1
y∈/ VT (n) (an invalid codeword). there be L0 0’s and L1 1’s to the left of x, and R0 0’s and
R 1’s to the right of x (with p = 1+L +L ). Also, let
1 0 1
The shaded row in Table I corresponds to a combination
ω denote the weight (number of 1’s) of c(cid:48). Calculate the new
of a deletion error and an insertion error that resulted in an checksum (cid:80)n−1ic(cid:48).
invalid codeword. Now if x=i=01, thei new checksum is R less than (cid:80)n ic .
Step 4: Our extended codeword can correct a single shift 1 i=1 i
We note that R ≤ω. If x=1, the new checksum is p+R
1 1
erroranddecodethedata.First,weneedtounderstandhow lessthan(cid:80)n ic .Wenotethatp+R =1+L +L +R =
to recover data in the error-free case. i=1 i 1 0 1 1
1+ω+L which is greater than ω.
0
Error-free decoding: If no error is detected using the delim-
So if the deficiency in the checksum is less than or equal
iter bits and the checksum, the k = n−(cid:96)−1 data bits are
to ω, we restore the codeword by adding a 0 just to the left
simply retrieved from the positions in c that are not powers
of the rightmost R 1’s. Otherwise, we restore the codeword
1
of two, i.e. positions 3,5,6,7,9, etc. So the only remaining
by adding a 1 just to the right of the leftmost L 0’s.
0
task is to correct a shift error when it happens.
Correctingadeletionerror:Deletionerrorscanbecorrected APPENDIXB
using the elegant algorithm proposed by Levenshtein [16], DERIVATIONOFTABLEI
[17]. This algorithm is presented below, and we refer the In this appendix we describe how the combination of a
reader to [18] for a mathematical analysis. VT code and six delimiter bits can be used to to identify
two deletions, or a deletion and a repetition. The other cases positions m−5,m−4,m−3, and m−2 we can observe
appearing in Table I can be derived using similar arguments. two possibilities as described below. The case in which one
Two deletions: There are three cases to consider as listed repetition happens in the VT code and one deletion in the
below. delimiter bits can be explained similarly.
1) Two deletions in the VT code: In this case, in positions 1) 1000: According to Table I, we declare a single deletion.
m−5,m−4,m−3, and m−2 we observe 0000 and SincetheVTcodeonlycontainsasingleshifterror,data
position m−1 corresponds to the first bit of the next can be reliably recovered.
extended codeword. In this case, we declare erasure and 2) 1100: If the checksum is zero modulo n+1, we were
we use the outer-code to resolve this case. lucky and the deletion followed by introducing the first
2) Two deletions in the delimiter bits: For this scenario, bit of the delimiter bits in position m−6 resulted in the
the VT code is unaffected. However, we will declare correct codeword. If the checksum is not zero modulo
either one or two deletions as we cannot identify the n+1, we declare erasure and we use the outer-code to
locationoftheseerrors.Inpositionsm−5,m−4,m−3, resolve this case.
andm−2wecanobservethreepossibilitiesasdescribed
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