components :: opti :: dataSheets :: 82C497 OPTi-DXBB 199201

36 Pages·199201·0.9 MB·English

I I
OPii'S DXBB 82C497 Vl.2 PREIJMINARY
OPTi-DXBB PC/A T Chipset
(82C497)
PRELIMINARY
82C497 DATA BOOK
Version 1.2
January 16, 1992
PAGEl
..
>
:: i-=
....
%
i~
'.!.
u
u
;F
;:
..
•
..
'.%.
0
:t
!..
.u.
u
"
"I '
I
.".:.
..
..
;:
-'-
;:
-.-
..
•
..
..
: •
..
0
:t ..
•
i".i.'
-
u ..
..
!
.I.
7
;:
....I. ...
..
..
"u_•, •0... ..~"'00.... ua00.•. .8.u. •.,.a•....; ..•u•.. •i..u. .0~..... i.. . .-0uu•.. 0~.".u•.. !."> ~..
Vl.2 PRELIMINARY OPTi'S DXBB 82C497
DISCLAIMER
Tilis specification is subject to change without notice. OPTi Inc. assumes no
responsibility for any errors contained within.
Copyright by ~PTi Inc. All rights reserved.
OPTi Inc.
2525 Walsh Avenue Santa Cara, CA 95051. USA
Tel: [phone]
Fax: [phone]
PAGE· 3
I I
OPTi'S DXBB 82C497 Vl.2 PRELIMINARY
1.0 FEATURES
• 386 and 486 CPU interface
• Isolates the CPU bus from Local bus, more reliable system
operation at high speed
• Asynchronous handshaking between CPU bus and Local bus;
•,
fixed base-board speed with upgradeable CPU card speed
• Direct map write back cache with one level write buffer and
16-byte line size
• Programmable 2-1-1-1,3-1-1-1,2-2-2-2 or 3-2-2-2 burst read cycle
• Programmable cache write hit 0 or 1 wait state
• Optional Dirty bit
• Supports 32K - 256K cache size for 386 cache system
• Support 64K - 512K cache size for 486 cache system
• Provides TAG and Dirty RAM test capability
• Built-in TAG auto-invalidation circuitry
• Two programmable non-cacheable regions
• Option for write-protected, cacheable Video BIOS
• Cacheable AT bus memory space
• 8042 emulation for fast CPU-reset and gateA20 generation
• 1X clock source support for systems from 16 MHZ to 50 :MHZ
• 160-pin plastic quad flat package
I
PAGE 1-1
I
Vl.2 PRELIMINARY OPTi'S DXBB 82C497
OPTi DXBB System Diagram
r---- ..
I I
80386DX
I Optional I
80486SX
I NPX I
t. .... - _ 80486DX
J
CPU Bus
Control
----------~_L-___J_~~---1~-------------"i"-+f---1±i--,~----------------------~~Address
r---- ..
i ~ab
l l /'""--------I-±-I_±_- --------~-,
r Data \
i i
;~b~ Con~~ M~
Buffer SRAM
_;,,., __.. _ 1.:..~-·- ~-_. _. __'- -__-__. --1'- -_o_ara_ __- _ __Aci _·...·....~.- .._ 1~1 -· ··.··. _. ..... ...._ .... ..._ ... ··. ·..,.__@__PT_i o_N__~_ _-_ _-_ ._.J_ ______ ..IControl
Address
Dab
l
Data
Memory MAs
Controls
ISA Bus
Figurel
PAGE s-
I I
OPii'S DXBB 82C497 Vl.2 PRELIMINARY
2.0 INTRODUCTION
The OPTi 82C497 is a Direct Mapped Write Back cache controller with one
level write buffer that is an optional part of the DXBB (Building Bl~dc) Chip set
The DXBB also contains the 82C496 and the 82C206, which form the heart of the
system. The 82C497 is added to the DXBB chip set for cache based systems.
The OPTi 82C496 offers an upgradable CPU module base-board solution
for the 80386 or the 80486 PC/ AT system. By swapping the CPU module, the
vendor can configure the 82C496 driven base-board into various 32-bit AT
systems - 386 or 486 CPU, with cache or without cache and rated at 16Wiz
SOMHz.
For the Non-Cache systems, the CPU interfaces directly with the 82C496
and the local devices, like the local VGA controller or the local hard disk
adaptor.
For cache based systems the 82C497 (the cache controller) sits between the
CPU and the 82C496 and the local devices. All the high .frequency signals are "
isolated by the 82C497. This allows the base-board to run at a fixed speed (25 or
33MHz) - while the CPU and the Cache can run synchronously at any
determined rated speed. This provides a reliable upgrade method for the CPU
modules.
PAGE 0
I
Vl.2 PRELIMINARY OPTi'S DXBB 82C497
82496 SYSTEM
16/20/25 :MHz LOCAL BUS
0(31:0) A(31:2)
STATUS SIGNALS
CPU
DRAM
'386 I '486
64MB
CACHE/
NON-CACHE
DRAM CONTROL
r.------__::i CONTROL SICNALS !SA CONTROLS I
BUFFER
s
I OPTI .___
I ..--- ... A
82C496
I LOCAL DEVICES
I VGA/HARD DISK XDnS:OI !SA DATA BtJS
BUFFER B
L
u
'--
s
OPTi ROM
KBC
82C206
FIGURE2A
PAGE.7
I
I
OPTi'S DXBB 82C497 Vl.2 PRELIMINARY
82497 SYSTEM
16-SOMHz
25/33MHz
CPU BUS
LOCAL BUS
ADDRESS ADDRESS
STATUS DATA STATUS DATA
CPU
'386/'486
CACHE TAG
..
OPTi
NPX
srATUS 82497 SfATUS
'387/3167/4167
Cache
~tat IA!~
<Dl711! Cntrlr. lnl7ill
Df3l:SI
llUFF!ll
FIGURE2B
PAGE$
I
Vl.2 PRELIMINARY OPii'S DXBB 82C497
3.0 DESCRIPTION
The 82C497 is a direct write back cache control unit with one-level of
write buffers and a 16 byte line size. The cache controller can support cache sizes
from 32I< to 512!< with a cacheable address range of upto 64M. There is a
programmable option of 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 burst read cycles and
a cache write hit of 0 or 1 wait state. The 82C497 also provides asynchronous
handshaking between the CPU bus and the loci! bus to enable a fixed base
board speed with variable CPU unit speeds. The controller also supports the
Dirty bit option and has TAG and Dirty RAM test capability.
The 82C497 consists of six functional blocks: 1) CPU interface 2) Local Bus
Interface 3) Cache control logic 4) Reset generation and Keyboard emulation
logic S) Data &: Address Latches 6) Programmable Registers.
3.1 CPU Interface
The CPU interface monitors and relays the particular cycles.to the related_ _
control units and returns the READY signal back to the CPU when the cycle is
completed.
1. Numeric Co-Processor (NPX) cycles
The NPX being installed or not determines the way the '497 treats the NPX
cycles. If the NPX is not installed, the '497 treats any NPX cycle as an AT cycle. If
the NPX is installed, the '497 will not take any action, when the CPU accessess
any of the NPX address spaces, except re-synchronizing the NPX READY before
sending it back to the CPU.
2. Cache cycles
The cache hit cycle is handled by the cache control logic. The cache read
miss cycle is also turned over to the cache control logic, after the external cache is
filled from the DRAM on the Local bus. The CPU status signals including ADS#
do not go to the Local bus if there is a ca~e hit cycle .
. PAGE 1 .
I
I
OPii'S DXBB 82C497 Vl.2 PRELIMINARY
82C497 BLOCK DIAGRAM
ADDRESS
STATUS DATA
PROGRA!VWABLE I<BD EMULATION
REGISTERS & RE.5ET LOGIC
LOCAL BUS
CPU INTERFACE
STATE 1V1ACHINE
STATE-1\t1ACHINE
CACHE
CONTROLLER DATA & ADDRESS
LATCHES
FIGURE3A
PAGE 10