cmos class e power amplifier modelling and design including channel resistance effects a thesis ...

111 Pages·2004·1.45 MB·English

CMOS CLASS E POWER AMPLIFIER MODELLING AND DESIGN
INCLUDING CHANNEL RESISTANCE EFFECTS

A THESIS SUBMITTED TO
THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES
OF
MIDDLE EAST TECHNICAL UNIVERSITY

BY

(cid:1)BRAH(cid:1)M DEM(cid:1)R

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR
THE DEGREE OF MASTER OF SCIENCE
IN
ELECTRICAL AND ELECTRONICS ENGINEERING

DECEMBER 2004
Approval of the Graduate School of Natural and Applied Sciences

Prof. Dr. Canan Özgen
Director

I certify that this thesis satisfies all the requirements as a thesis for the degree of
Master of Science.

Prof. Dr. (cid:1)smet Erkmen
Head of Department

This is to certify that we have read this thesis and that in our opinion it is fully
adequate, in scope and quality, as a thesis for the degree of Master of Science.

Prof. Dr. Canan TOKER Assist. Prof. Dr. (cid:2)im(cid:3)ek DEM(cid:1)R
Co-Supervisor Supervisor

Examining Committee Members

Prof. Dr. Altunkan HIZAL (METU,EE)
Assist. Prof. Dr. (cid:2)im(cid:3)ek DEM(cid:1)R (METU,EE)
Prof. Dr. Canan TOKER (METU,EE)
Prof. Dr. Murat A(cid:2)KAR (METU,EE)
Umut AYDIN (ORTANA LTD.
PLAGIARISM

I hereby declare that all information in this document has been obtained and
presented in accordance with academic rules and ethical conduct. I also declare
that, as required by these rules and conduct, I have fully cited and referenced
all material and results that are not original to this work.

(cid:1)brahim Demir

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ABSTRACT

CMOS CLASS E POWER AMPLIFIER
MODELLING AND DESIGN
INCLUDING CHANNEL RESISTANCE EFFECTS

DEM(cid:1)R, (cid:1)brahim

M.S., Department of Electrical and Electronics Engineering
Supervisor : Assist. Prof. Dr. (cid:2)im(cid:3)ek DEM(cid:1)R
Co-Supervisor : Prof. Dr. Canan TOKER

December 2004, 96 Pages

CMOS is the favorite candidate process for the high integration of the
wireless communication IC blocks, RF frontend and digital baseband circuitry. Also
the design of the RF power amplifier stage is the one of the most important part of
the RF CMOS circuit design. Since high frequency and high power simultaneously
exists on this stage, devices works on the limits of the process. Therefore standard
device models may not be valid enough for a successful design. In the thesis high
frequency passive device and MOS transistor models for the CMOS process searched
though the literature and presented. Besides, different structures of the inductors are
investigated for the best quality factor for the chosen process.
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Class E power amplifiers can reach very high efficiencies and they are very
suitable for the low power applications. After the derivation of the classical Class E
equations is presented, a new Class E circuit model including MOS transistor’s
channel resistance is developed and new sets of equations are obtained for the model.
Circuit parameters are determined using numerical methods. Class E circuit
simulations with these new parameters and earlier parameters are compared.
Finally, a 100mW 2.4GHz Class E power amplifier is designed and simulated
targeting Bluetooth applications. In this design, Class E circuit parameters are
determined for AMS CMOS 0.35um process MOS transistor including the channel
resistance. Simulations are performed using Cadence/BSIM3v3 and OrCad PSPICE.

Keywords: Class E Amplifier, Power Amplifier, RF CMOS, Modeling, Channel
Resistance Effects
v
ÖZ

CMOS E-SINIFI GÜÇ YÜKSELTEC(cid:1)N(cid:1)N
KANAL D(cid:1)RENÇ ETK(cid:1)LER(cid:1)N(cid:1) (cid:1)ÇEREN
MODELLEMES(cid:1) VE TASARIMI

DEM(cid:1)R, (cid:1)brahim

Yüksek Lisans,Elektrik ve Elektronik Mühendisli(cid:4)i Bölümü
Tez Yöneticisi : Yar.Doç. Dr. (cid:2)im(cid:3)ek DEM(cid:1)R
Ortak Tez Yöneticisi : Prof. Dr. Canan TOKER

Aralık 2004, 96 Sayfa

CMOS süreci, radyo frekansı ön uç ve sayısal temel band devreleri gibi
kablosuz haberle(cid:3)me tümdevre birimlerinin bile(cid:3)tirilmesi için en uygun adaydır.
Radyo frekansı güç yülselteç katı tasarımı ise RF CMOS tümdevre tasarımındaki en
önemli kısımlardan biridir. Bu katta hem yüksek frekans hem de yüksek güç bir
arada bulundu(cid:4)undan, devre elemanları kullanılan sürecin limitlerinde çalı(cid:3)ırlar. Bu
nedenden standart modeler ba(cid:3)arılı bir tasarım için yeterli olmayabilir. CMOS süreci
için yüksek frekansta pasif eleman ve MOS transistor modelleri ara(cid:3)tırıldı ve
toplandı. Ayrıca seçilen süreçde en uygun kalite faktörü için de(cid:4)i(cid:3)ik bobin yapıları
incelendi.
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E sınıfı güç yükselticileri çok yüksek verimlilikte çalı(cid:3)abilirler ve dü(cid:3)ük güç
uygulamaları için çok uygundurlar. Bu tezde klasik E sınıfı güç yükselteçlerinin
literatürde yer alan denklemlerinin çıkarılması verildikten sonra MOS transistörünün
kanal direncini de içeren yeni bir model geli(cid:3)trildi ve bir denklem seti elde edildi.
Devre elemanlarının de(cid:4)erleri numerik yöntemler kullanılarak hesaplandı. Yeni
de(cid:4)erlerle ve eski de(cid:4)erlerle yapılan simulasyonlar kar(cid:3)ıla(cid:3)tırıldı.
Son olarak MOS transistor kanal direncini hesaba katan bu yeni yöntem
kullanılarak, Bluetooth uygulamalarına yönelik 100mW 2.4GHz E sınıfı bir güç
yükselteci AMS CMOS 0.35um süreci kullanılarak tasarlandı ve similasyonu
gerçekle(cid:3)tirildi. Similasyonlarda Cadence/BSIM3v3 ve OrCad PSPICE programları
kullanıldı.

Anahtar Kelimeler: E Sınıfı Güç Yükselteci, Güç Yükselteci, RF CMOS,
Modelleme, Kanal Direnç Etkileri
vii
ACKNOWLEDGEMENTS

I wish to express my sincere gratitude to Prof. Dr. Canan Toker and Assist.
Prof. Dr. (cid:2)im(cid:3)ek Demir for their supervision, valuable guidance and helpful
suggestions.

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TABLE OF CONTENTS

PLAGIARISM.....................................................................................................III
ABSTRACT.........................................................................................................IV
ÖZ.........................................................................................................................VI
ACKNOWLEDGEMENTS..............................................................................VIII
TABLE OF CONTENTS.....................................................................................IX
LIST OF TABLES..............................................................................................XII
LIST OF FIGURES..........................................................................................XIII
CHAPTER
1 INTRODUCTION................................................................................................1
1.1 SCOPE AND OBJECTIVE...............................................................................1
1.2 ORGANIZATION OF THE THESIS...................................................................2
2 RF CMOS TECHNOLOGY................................................................................4
2.1 INTRODUCTION...........................................................................................4
2.2 PASSIVE COMPONENTS...............................................................................6
2.2.1 Interconnects.....................................................................................6
2.2.2 On Chip Resistors..............................................................................8
2.2.2.1 Polysilicon Resistor.......................................................................8
2.2.2.2 Diffused Resistor...........................................................................9
2.2.2.3 Well Resistor.................................................................................9
2.2.2.4 MOS Transistor Resistor................................................................9
2.2.2.5 Metal Resistor..............................................................................10
2.2.3 On Chip Capacitors..........................................................................10
2.2.3.1 Parallel Plate Capacitor................................................................11
2.2.3.2 Lateral Capacitor.........................................................................12
2.2.3.3 Gate (MOS) Capacitor.................................................................14
2.2.3.4 Junction Capacitors......................................................................14
2.2.4 On Chip Inductors...........................................................................15
2.2.4.1 Planar Spiral Inductors.................................................................17
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2.2.4.2 Planar Solenoidal Inductors..........................................................20
2.2.4.3 Bond Wire Inductors....................................................................20
2.3 ACTIVE COMPONENTS: MOSFET DEVICES...............................................20
2.3.1 Linear Region..................................................................................21
2.3.2 Saturation Region............................................................................23
2.3.3 Channel Length Modulation.............................................................23
2.3.4 Body Effect.....................................................................................23
2.3.5 Capacitance Model..........................................................................24
2.3.6 High Frequency Figures of Merits....................................................26
2.3.7 Short Channel Effects......................................................................26
2.3.8 Small Signal Model of the MOSFET...............................................27
2.3.9 Developing High Frequency Simulation Models of the MOSFET....28
3 CLASS E POWER AMPLIFIERS....................................................................30
3.1 INTRODUCTION.........................................................................................30
3.2 HIGH EFFICIENCY SWITCHING POWER AMPLIFIERS...................................32
3.3 CLASS E POWER AMPLIFIER CIRCUIT TOPOLOGY......................................34
3.4 BASIC CIRCUIT EQUATIONS......................................................................34
3.4.1 Basic Relationships..........................................................................36
3.4.2 Fourier Analysis..............................................................................38
3.4.3 Power and Efficiency.......................................................................40
3.4.4 Device Stress...................................................................................41
3.4.5 High-Efficiency Operation...............................................................42
4 CLASS E CHANNEL RESISTANCE MODEL...............................................46
4.1 INTRODUCTION.........................................................................................46
4.2 DERIVING EQUATIONS..............................................................................48
4.2.1 Base Equations................................................................................49
4.2.2 Sine Transformation........................................................................50
4.2.3 Cosine Transformation.....................................................................52
4.2.4 High Efficiency Conditions..............................................................53
4.2.5 Obtaining The High Efficiency Solution..........................................55
4.2.6 The Efficiency.................................................................................59
4.2.7 Solution Results...............................................................................60
4.3 SIMULATION RESULTS..............................................................................66
x