Circuits for blind ADC-based CDRs and frequency detectors by Mohammad Sadegh Jalali A thesis ...

151 Pages·2014·14.17 MB·English

Circuits for blind ADC-based CDRs
and frequency detectors
by
Mohammad Sadegh Jalali
A thesis submitted in conformity with the requirements
for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
Copyright (cid:13)c 2015 by Mohammad Sadegh Jalali
Circuits for blind ADC-based CDRs
and frequency detectors
Mohammad Sadegh Jalali
Doctor of Philosophy, 2015
Graduate Department of Electrical and Computer Engineering
University of Toronto
Abstract
This thesis presents three contributions in the area of clock and data recovery (CDR).
Two of these three contributions focus on the design of frequency detection mechanisms
for reference-less half-rate clock and data recovery circuits, while the third one focuses
on the design of blind ADC-based CDRs.
While conventional CDR architectures for phase and frequency detection are dual
loop, the interaction between the frequency detection loop and the phase detection loop
can interfere with phase locking. Furthermore, the frequency detector, typically de-
activated after lock, occupies area. This thesis introduces two new architectures for
reference-less CDRs which perform frequency detection by adjusting the phase error of
the phase detector. This enables the phase detector to deal with frequency offset, as well
as phase offset. The feasibility of these two 10Gb/s CDRs are demonstrated through
chip fabrications in Fujitsu 65nm CMOS technology and measurement results.
The third contribution of this thesis is in the area of blind ADC-based CDRs. While
the design simplicity of these CDRs significantly reduces their time to market, their high
power consumption limits their application. This thesis studies the architecture of these
CDRs with the goal of minimizing their power consumption. We will show that for
ii
a given analog power consumption, the optimum oversampling ratio is 2.8 (≈3). The
digital CDR is also redesigned to lower the power consumption of digital equalization. A
5Gb/s CDR was fabricated in Fujitsu 65nm CMOS technology and measurement results
show a factor of 2 of power reduction, with improved performance.
iii
Acknowledgments
First of all, I would like to express my deepest gratitude to my supervisor, Professor Ali
Sheikholeslami, for his guidance, patience and support. He never failed to impress me
with his ability to take a complicated problem and explain it in a way that is extremely
easy to understand. I am sorry if some of my figure revisions went to version 20 and
thank you for being so patient with me. Ali is a great researcher and an excellent teacher
and I am thankful to him for all his help.
I would like to thank Dr. Hirotaka Tamura and Mr. Masaya Kibune from Fujitsu
Laboratories Limited (FLL) for their help during the course of my PhD. It was a pleasure
for us to be their hosts once or twice a year. Thank you for patiently sitting through our
brain storming sessions and for giving us feedback on our sometimes random ideas.
I am thankful to the members of my Ph.D. oral examination committee and also the
members of my Ph.D. Proposal examination committee: Prof. Tony Chan Carusone,
Prof. Antonio Liscidini, Prof. David Johns and Prof. Wai Tung Ng, Prof. Raviraj Adve
and also my external thesis examiner: Prof. Pavan Kumar Hanumolu for their valuable
feedback.
I had the pleasure of going through my Ph.D. journey with many great friends. In
particular, I spent hours “chilling” with Shayan Shahramian, Ravi Shivnaraine, Safeen
Huda, Alireza Sharif and Alireza Bakhtiari. As Ravi said perfectly in the acknowledge-
ment section of his thesis, thanks for these awesome friends for being always in for any
fun activity possible. Thanks guys for being around in both the fun times and the hard
times. Thanks to Clifford Ting and Joshua Liang for being the perfect lab mates in
iv
“Fuji” room, and sorry if I made too much noise (both of them currently own a Bose
noise cancelling headphone).
I would also like to extend my gratitude to my friends in BA5000 and also to the
former and current graduate students of Ali group for all the great times and for all the
fun and (sometimes) random discussions. I am specially thankful to (I know I will leave
some names out) Aynaz Vatankhah, Mario Milicevic, Rocky Dong, Meisam Zargham,
Zeynep Lulec, Dustin Dunwell, Wahid Rahman, Alireza Nilchi, Behrooz Abiri, Michal
(this spelling is correct) Fulmyk, Shahriar Shahramian, Farhad Ramezankhani, Luke
Wang, Dawei Song and Rosana Murugesu.
Last but most certainly not least, I would like to extend my deepest appreciation to
mywonderfulparents,mylovelybrotherandsisterforinspiringmewiththeirenthusiasm,
for believing in me and encouraging me, for their endless love and support, and for being
around whenever I needed them the most. They have always been the greatest source of
inspiration for me, and I dedicate this thesis to them.
v
Contents
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Background: ADC-Based Receivers 7
2.1 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Data Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Channel response . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3 Linear Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.4 Decision-Feedback Equalizer . . . . . . . . . . . . . . . . . . . . . 13
2.2 Clock and Data Recovery Circuits . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Phase-tracking ADC-based CDRs . . . . . . . . . . . . . . . . . . 16
2.2.2 Blind ADC-Based CDR . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2.1 2x Blind ADC-Based CDR . . . . . . . . . . . . . . . . 18
2.2.2.2 DFE in a 2x blind ADC-based CDR . . . . . . . . . . . 20
2.2.2.3 Handling Frequency Offset . . . . . . . . . . . . . . . . . 22
2.2.2.4 1.45x Blind ADC-Based CDR . . . . . . . . . . . . . . . 22
2.2.2.5 1x Blind ADC-Based CDR . . . . . . . . . . . . . . . . 23
2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
vi
3 Proposed 3x blind ADC-based Receiver 26
3.1 Interpolation-First Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Voltage-Phase Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Receiver Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.1 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.2 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 38
3.3.3 ADC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.4 Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.5 Digital CDR Design . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.1 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.2 Digital Receiver Without CLTE . . . . . . . . . . . . . . . . . . . 52
3.4.3 Digital Receiver With CLTE . . . . . . . . . . . . . . . . . . . . . 54
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Frequency Detection in Phase-Tracking CDRs 58
4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1.1 CDR Operation in the Presence of Frequency Offset . . . . . . . . 61
4.1.2 Analysis of CDR transient . . . . . . . . . . . . . . . . . . . . . . 65
4.2 Frequency Detectors in Referenced CDRs . . . . . . . . . . . . . . . . . . 68
4.3 Frequency Detectors in Referenceless CDRs . . . . . . . . . . . . . . . . 70
4.3.1 Rotational Frequency Detectors . . . . . . . . . . . . . . . . . . . 71
4.3.2 Frequency Sweeping FD . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.3 Stochastic Frequency Detectors . . . . . . . . . . . . . . . . . . . 77
4.3.4 Frequency Detection Based on “Phase Reset” . . . . . . . . . . . 79
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
vii
5 Clock-Phase Selection Scheme for a FD 81
5.1 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Lock Time Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3 CDR Architecture and Implementation . . . . . . . . . . . . . . . . . . . 87
5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6 Data-Phase Selection Scheme for a FD 95
6.1 Proposed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7 Conclusions 113
7.1 Research Contributions and Collaborations . . . . . . . . . . . . . . . . . 114
7.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.2.1 Blind ADC-based CDRs . . . . . . . . . . . . . . . . . . . . . . . 115
7.2.2 Single-loop Referenceless Phase-tracking CDRs . . . . . . . . . . 117
References 117
viii
List of Tables
3.1 Comparison of Digital CDR results . . . . . . . . . . . . . . . . . . . . . 56
6.1 Comparison of CDR results . . . . . . . . . . . . . . . . . . . . . . . . . 112
ix
List of Figures
1.1 International technology roadmap for semiconductors (ITRS) projections
for the growth in data rate and pin number . . . . . . . . . . . . . . . . 2
2.1 Basic wireline transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Basic CDR types: (a) phase-tracking CDR (b) phase-tracking ADC-based
CDR (c) blind ADC-based CDR . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 (a) NRZ data waveforms for an example “1011” pattern (b) power spectral
density for a random binary sequence . . . . . . . . . . . . . . . . . . . . 10
2.4 Channel response of Tyco FR4 channels with various length . . . . . . . 10
2.5 Response of the 11.5” channel to a 10Gb/s pulse . . . . . . . . . . . . . . 11
2.6 Principle operation of linear equalizers . . . . . . . . . . . . . . . . . . . 12
2.7 (a) Block Diagram of a CTLE (b) capacitive source-degenerated differen-
tial pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8 Block Diagram of a DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.9 (a) Split summation DFE (b) loop-unrolled DFE . . . . . . . . . . . . . 16
2.10 Digital CDR in phase-tracking ADC-based CDR . . . . . . . . . . . . . . 17
2.11 Example of (a) pulse response and (b) MM function [57] . . . . . . . . . 18
2.12 2x blind ADC-based CDR; architecture and example . . . . . . . . . . . 19
2.13 Definition of Φ , Φ and Φ . . . . . . . . . . . . . . . . . . . . . 19
X AVG PICK
2.14 Data decision operation in the presence of (a) no jitter (b) jitter example
1 (b) jitter example 2 [15] . . . . . . . . . . . . . . . . . . . . . . . . . . 20
x