ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 256KB Flash/64KB RAM, 10 TIMs, 1 ADC, 11 comm ...

53 Pages·2013·1.53 MB·English

STM32F401xB STM32F401xC
ARM Cortex-M4 32b MCU+FPU, 105 DMIPS,
256KB Flash/64KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces
Data brief
• 1×12-bit, 2.4MSPS A/D converter: up to 16
channels
• General-purpose DMA: 16-stream DMA
WLCSP49 U(7F Q× F7P mNm48) FBGA controllers with FIFOs and burst support
(3 x 3 mm) • Up to 10 timers: up to six 16-bit, two 32-bit
LQFP100 (14 × 14 mm) UFBGA100(1) timers up to 84MHz, each with up to 4
LQFP64 (10 × 10 mm) (7 x 7 mm)
IC/OC/PWM or pulse counter and quadrature

1. UFBGA100 will be available soon. (incremental) encoder input, two watchdog
timers (independent and window)
Features
• Debug mode
• Core: ARM 32-bit Cortex™-M4 CPU with FPU, – Serial wire debug (SWD) & JTAG interfaces
Adaptive real-time accelerator (ART – Cortex-M4 Embedded Trace Macrocell™
Accelerator™) allowing 0-wait state execution • Up to 79 I/O ports with interrupt capability
from Flash memory, frequency up to 84MHz,
– All IO ports 5 V tolerant
memory protection unit, 105DMIPS/
– Up to 76 fast I/Os up to 42MHz
1.25DMIPS/MHz (Dhrystone 2.1), and DSP
instructions • Up to 11 communication interfaces
• Memories – Up to 3 × I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (2 x 10.5Mbit/s, 1 x
– Up to 256 Kbytes of Flash memory
5.25Mbit/s), ISO 7816 interface, LIN, IrDA,
– Up to 64Kbytes of SRAM
modem control)
• Clock, reset and supply management – Up to 4 SPIs (up to 42Mbits/s at f = 84
CPU
– 1.7 V (PDR OFF) or 1.8 V (PDR ON) to MHz), SPI2 and SPI3 with muxed full-
3.6V application supply and I/Os duplex I2S to achieve audio class accuracy
– POR, PDR, PVD and BOR via internal audio PLL or external clock
– 4-to-26MHz crystal oscillator – SDIO interface
– Internal 16 MHz factory-trimmed RC • Advanced connectivity
– 32 kHz oscillator for RTC with calibration – USB 2.0 full-speed device/host/OTG
– Internal 32 kHz RC with calibration controller with on-chip PHY
• Power consumption • CRC calculation unit
– Run: 137µA/MHz (peripheral off) • 96-bit unique ID
– Stop (Flash in Stop mode, fast wakeup • RTC: subsecond accuracy, hardware calendar
time): 50µA typ @ 25°C;
80µA max @25°C
Table 1. Device summary
– Stop (Flash in Deep power down mode):
Reference Part number
down to 11µA typ@ 25°C;
STM32F401xB STM32F401CB, STM32F401RB, STM32F401VB
40µA max @25°C
STM32F401xC STM32F401CC, STM32F401RC, STM32F401VC
– Standby: 2.4µA @25°C / 1.7V without
RTC; 12µA @85°C @1.7V
– V supply for RTC: 1µA @25°C
BAT
April 2013 DocID024025 Rev 1 1/53
For further information contact your local STMicroelectronics sales office. www.st.com 1
Table of contents STM32F401xB STM32F401xC
Table of contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 ARM® Cortex™-M4 with FPU core with embedded Flash and SRAM . . . 10
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 10
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . .11
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 13
3.10 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.12 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.14.1 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14.2 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.14.3 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.14.4 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14.5 Regulator ON/OFF and internal power supply supervisor availability . . 19
3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.16 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.17 V operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
BAT
3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.18.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM32F401xB STM32F401xC Table of contents
3.18.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.19 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.20 Universal synchronous/asynchronous receiver transmitters (USART) . . 24
3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.22 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.23 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.24 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 26
3.25 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 26
3.26 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.27 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1.1 WLCSP49 wafer level chip size package . . . . . . . . . . . . . . . . . . . . . . . 44
5.1.2 UFQFPN48 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . . . 46
5.1.3 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package . . . . . . . . . 47
6 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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List of tables STM32F401xB STM32F401xC
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F401xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 19
Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Comparison of I2C analog and digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. STM32F401xx WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Legend/abbreviations used in the pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. STM32F401xx pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. WLCSP49 wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 46
Table 13. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 48
Table 14. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . . 49
Table 15. Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STM32F401xB STM32F401xC List of figures
List of figures
Figure 1. STM32F401xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 15
Figure 4. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Startup in regulator OFF: slow V slope
DD
- power-down reset risen after V /V stabilization. . . . . . . . . . . . . . . . . . . . . . . . 18
CAP_1 CAP_2
Figure 6. Startup in regulator OFF mode: fast V slope
DD
- power-down reset risen before V /V stabilization . . . . . . . . . . . . . . . . . . . . . . 18
CAP_1 CAP_2
Figure 7. STM32F401xx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. STM32F401xx LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. STM32F401xx LQFP100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. WLCSP49 package dimensions (in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. WLCSP49 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 13. Recommended footprint (dimensions in mm)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 14. UFQFPN48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 47
Figure 16. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17. LQFP64 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 18. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . 49
Figure 19. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 20. LQPF100 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Introduction STM32F401xB STM32F401xC
1 Introduction
This databrief provides the description of the STM32F401xx line of microcontrollers.
The STM32F401xx data brief should be read in conjunction with the STM32F40xxx,
STM32F41xxx, STM32F42xxx, STM32F43xxx reference manual RM0344.
The reference manual is available from the STMicroelectronics website www.st.com. It
includes all information concerning Flash memory programming.
For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming
manual (PM0214) available from www.st.com.

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STM32F401xB STM32F401xC Description
2 Description
The STM32F401XX device family is based on the high-performance ARM® Cortex™-M4 32-
bit RISC core operating at a frequency of up to 84 MHz. Its Cortex-M4 with FPU core
features a Floating point unit (FPU) single precision which supports all ARM single-precision
data-processing instructions and data types. It also implements a full set of DSP instructions
and a memory protection unit (MPU) which enhances application security.
STM32F401xx devices incorporate high-speed embedded memories (Flash memory up to
256 Kbytes, up to 64Kbytes of SRAM), and up to 79 enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers
including one PWM timer for motor control, two general-purpose 32-bit timers. They also
feature standard and advanced communication interfaces.
• Up to three I2Cs
• Up to four SPIs
• Two full duplex I 2S peripherals. To achieve audio class accuracy, the I2S peripherals
can be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
• Three USARTs
• SDIO interface
• USB 2.0 OTG full speed interface
Refer to Table2: STM32F401xx features and peripheral counts for the peripherals available
for each part number.
The STM32F401xx devices operate in the –40 to +105°C temperature range from a 1.7
(PDR OFF) to 3.6V power supply. A comprehensive set of power-saving mode allows the
design of low-power applications.
These features make the STM32F401xx microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile phone sensor hub
Figure1 shows the general block diagram of the device family.
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Description STM32F401xB STM32F401xC

Table 2. STM32F401xx features and peripheral counts
Peripherals STM32F401xB STM32F401xC
Flash memory in Kbytes 128 256
SRAM in
System 64
Kbytes
General-
7
purpose
Timers
Advanced-
1
control
4/2 (full 4/2 (full
SPI/ I2S 3/2 (full duplex) 3/2 (full duplex)
duplex) duplex)
Communication I2C 3
interfaces
USART 3
SDIO - 1 - 1
USB OTG FS 1
GPIOs 36 50 81 36 50 81
12-bit ADC 1
Number of channels 10 16 10 16
Maximum CPU frequency 84 MHz
Operating voltage 1.7 to 3.6 V
Ambient temperatures: –40 to +85 °C/–40 to +105 °C
Operating temperatures
Junction temperature: –40 to + 125 °C
WLCSP49 WLCSP49
Package LQFP64 LQFP100 LQFP64 LQFP100
UFQFPN48 UFQFPN48
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STM32F401xB STM32F401xC Description
Figure 1. STM32F401xx block diagram

NJTRST, JTDI,
JTCK/SWCLK JTAG & SW MPU
JTDO/SWD, JTDO ETM NVIC
TRACECLK
TRACED[3:0] D-BUS
ARM Cortex -M4
84F MPHUz SI- -BBUUSS matrix 7S4M ACCEL/CACHE Fu2lp5a 6sto hK B
us- SRAM 64 KB
b
B
H
DMA2 8 Streams A AHB2 84 MHz (cid:40)(cid:57) (cid:53)(cid:51)(cid:34) (cid:38)(cid:47) (cid:36)(cid:36)(cid:45)(cid:48)
FIFO (cid:48) (cid:47)(cid:52)(cid:39)(cid:0)(cid:38)(cid:51) (cid:38)(cid:41) (cid:41)(cid:36)(cid:12)(cid:0)(cid:54)(cid:34)(cid:53)(cid:51)(cid:12)(cid:0)(cid:51)(cid:47)(cid:38)
DMA1 8 StreFaIFmOs AHB1 8 4 MHz VDD Power managmt
Voltage VDD = 1.7 to 3.6 V
3.r3e gtou l1 a.t2o rV (cid:8)(cid:17)(cid:48)(cid:14)(cid:24)(cid:36)(cid:0)(cid:84)(cid:50)(cid:79)(cid:0)(cid:0)(cid:47)(cid:19)(cid:14)(cid:38)(cid:22)(cid:38)(cid:0)(cid:54)(cid:9)
@VDDA @VDD VSS (cid:8)(cid:48)(cid:36)(cid:50)(cid:0)(cid:47)(cid:46)(cid:9)
PA[15:0] GPIO PORT A RC HS PreOseRt suSpeurpvpislyion VCAP
RC LS Int POR/PDR
PB[15:0] GPIO PORT B BOR VDDA, VSSA
PLL1&2 NRST
PVD
PC[15:0] GPIO PORT C
@VDDA@VDD
PD[15:0] GPIO PORT D XTAL OSC OSC_IN
4- 16MHz OSC_OUT
PE[15:0] GPIO PORT E MRAcelNoscAektG &T WDG 32K
control
PWR VBAT = 1.65 to 3.6 V
PH[1:0] GPIO PORT H interface
FCLKHCLKAPB2CLKAPB1CLKHB2PCLKHB1PCLK LS XTRAT@LC 3V2B kAHTz OOSSCC3322__IONUT
AA AWU ALARM_OUT
LS Backup register STAMP1
CRC
TIM2 32b 4 channels, ETR as AF
TIM3 16b 4 channels, ETR as AF
DMA2 DMA1
112 AF EXT IT. WKUP TIM4 16b 4 channels, ETR as AF
(cid:36)(cid:59)(cid:23)(cid:26)(cid:16)(cid:61) (cid:51)(cid:36)(cid:41)(cid:47)(cid:0)(cid:15)(cid:0)(cid:45)(cid:45)(cid:35) (cid:38)(cid:47) AHB/APB2 AHB/APB1 TIM5 32b 4 channels
(cid:35)(cid:45)(cid:36)(cid:12)(cid:0)(cid:35)(cid:43)(cid:0)(cid:65)(cid:83)(cid:0)(cid:33)(cid:38) (cid:38)(cid:41)
4 compl. channels TIM1_CH1[1:4]N,
4 channels TIM1_CH1[1:4]ETR, TIM1 / PWM16b
BKIN as AF
smcard RX, TX as AF
2 channels as AF TIM9 16b USART2 irDA CTS, RTS as AF
1 channel as AF TIM10 16b SP2/I2S2 MNSOSS/IW/SSD,, MMCISKO a/sS DAF_ext, SCK/CK
WWDG
RCSS1XCTC ,ScKK MMTh,R,, aXOORNNXn,TSSSS ,nC SIITSSe,,K Xl MMa aa a,as ssIIsC SSs A AA AKOOAFFFF,F,, sisirrmDmDAcAcaarrddUUTSSSSIAAMPPRRII1411TT16 16b APB2 60MHz APB2 84 MHz APB1 30MHz APB1 42 MHz (max) III222CCSC2P31//3/SSS/MMIM2BBSBUU3USSS MNSSSCCCSOSLLLS,,,/ IWSSS/SDDDSDAAA,, M,,,M SSSCIMMMSKOBBB aAAA/sS aaaDAsssF_ AAAexFFFt, SCK/CK
VDDREF_ADC UTeSmApReTra 2tuMrBe pssensor
10 analog inputs ADC1 IF
@VDDA
MS31144V1
1. The timers connected to APB2 are clocked from TIMxCLK up to 84 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 42MHz.
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Functional overview STM32F401xB STM32F401xC
3 Functional overview
®
3.1 ARM Cortex™-M4 with FPU core with embedded Flash and
SRAM
The ARM Cortex-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M4 with FPU 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F401xx family is compatible with all ARM tools and software.
Figure1 shows the general block diagram of the STM32F401xx family.
Note: Cortex-M4 with FPU is binary compatible with Cortex-M3.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex™-M4 with FPU processors. It balances the inherent performance
advantage of the ARM Cortex-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 105DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 84 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
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