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About 10 Ddecs Multiplier
This document discusses methods for synthesizing reversible multiplier circuits. It presents three new methods that address the drawbacks of previous approaches by reducing the number of circuit lines and improving scalability. The methods are evaluated based on the number of circuit lines, gates, quantum cost, and transistor costs. Reversible logic is motivated by applications in low-power design and quantum computation.
Detailed Information
| Author: | ['skarrys5'] |
|---|---|
| Publication Year: | 2017 |
| Pages: | 6 |
| Language: | English |
| Format: | |
| Price: | FREE |
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