Static Timing Analysis for Nanometer Designs: A Practical Approach

588 Pages·2009·3.35 MB·English

by  Rakesh Chadha

Static Timing Analysis for
Nanometer Designs
A Practical Approach
J. Bhasker • Rakesh Chadha

Static Timing Analysis for
Nanometer Designs

A Practical Approach
J. Bhasker Rakesh Chadha
eSilicon Corporation eSilicon Corporation
1605 N. Cedar Crest Blvd. 890 Mountain Ave
Suite 615 New Providence, NJ 07974, USA
Allentown, PA 1810 3, USA [email protected]
[email protected]
ISBN 978-0-387-93819-6 e-ISBN 978-0-387-93820-2
DOI: 10.1007/978-0-387-93820-2

Library of Congress Control Number: 2009921502

 Springer Science+Business Media, LLC 2009
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
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trademarks, service marks and similar terms, even if they are not identified as such, is not to
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rights.
While the advice and information in this book are believed to be true and accurate at the
date of going to press, neither the authors nor the editors nor the publisher can accept any
legal responsibility for any errors or omissions that may be made. The publisher makes no
warranty, express or implied, with respect to the material contained herein.

Some material reprinted from “IEEE Std. 1497-2001, IEEE Standard for Standard Delay
Format (SDF) for the Electronic Design Process; IEEE Std. 1364-2001, IEEE Standard
Verilog Hardware Description Language; IEEE Std.1481-1999, IEEE Standard for
Integrated Circuit (IC) Delay and Power Calculation System”, with permission from IEEE.
The IEEE disclaims any responsibility or liability resulting from the placement and use in
the described manner.
Liberty format specification and SDC format specification described in this text are
copyright Synopsys Inc. and are reprinted as per the Synopsys open-source license
agreement.
Timing reports are reported using PrimeTime which are copyright © <2007> Synopsys, Inc.
Used with permission. Synopsys & PrimeTime are registered trademarks of Synopsys, Inc.
Appendices on SDF and SPEF have been reprinted from “The Exchange Format Handbook”
with permission from Star Galaxy Publishing.

Printed on acid-free paper.

springer.com
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv
CHAPTER 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 NanometerDesigns........................................1
1.2 WhatisStaticTimingAnalysis?..............................2
1.3 WhyStaticTimingAnalysis?................................4
CrosstalkandNoise,4
1.4 DesignFlow .............................................5
1.4.1 CMOSDigitalDesigns .............................5
1.4.2 FPGADesigns....................................8
1.4.3 AsynchronousDesigns..............................8
1.5 STAatDifferentDesignPhases..............................9
1.6 LimitationsofStaticTimingAnalysis .........................9
1.7 PowerConsiderations.....................................12
1.8 ReliabilityConsiderations..................................13
1.9 OutlineoftheBook.......................................13
CHAPTER 2: STA Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 CMOSLogicDesign......................................15
2.1.1 BasicMOSStructure..............................15
2.1.2 CMOSLogicGate................................16
2.1.3 StandardCells ...................................18
2.2 ModelingofCMOSCells..................................20
2.3 SwitchingWaveform .....................................23
v
CONTENTS
2.4 PropagationDelay........................................ 25
2.5 SlewofaWaveform...................................... 28
2.6 SkewbetweenSignals .................................... 30
2.7 TimingArcsandUnateness ................................ 33
2.8 MinandMaxTimingPaths ................................ 34
2.9 ClockDomains.......................................... 36
2.10 OperatingConditions ..................................... 39
CHAPTER 3: Standard Cell Library . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 PinCapacitance.......................................... 44
3.2 TimingModeling ........................................ 44
3.2.1 LinearTimingModel.............................. 46
3.2.2 Non-LinearDelayModel........................... 47
ExampleofNon-LinearDelayModelLookup,52
3.2.3 ThresholdSpecificationsandSlewDerating............ 53
3.3 TimingModels-CombinationalCells........................ 56
3.3.1 DelayandSlewModels............................ 57
PositiveorNegativeUnate,58
3.3.2 GeneralCombinationalBlock....................... 59
3.4 TimingModels-SequentialCells ........................... 60
3.4.1 SynchronousChecks:SetupandHold................. 62
ExampleofSetupandHoldChecks,62
NegativeValuesinSetupandHoldChecks,64
3.4.2 AsynchronousChecks............................. 66
RecoveryandRemovalChecks,66
PulseWidthChecks,66
ExampleofRecovery,RemovalandPulseWidthChecks,67
3.4.3 PropagationDelay................................ 68
3.5 State-DependentModels................................... 70
XOR,XNORandSequentialCells,70
3.6 InterfaceTimingModelforaBlackBox...................... 73
3.7 AdvancedTimingModeling................................ 75
3.7.1 ReceiverPinCapacitance .......................... 76
SpecifyingCapacitanceatthePinLevel,77
SpecifyingCapacitanceattheTimingArcLevel,77
3.7.2 OutputCurrent................................... 79
vi
CONTENTS
3.7.3 ModelsforCrosstalkNoiseAnalysis..................80
DCCurrent,82
OutputVoltage,83
PropagatedNoise,83
NoiseModelsforTwo-StageCells,84
NoiseModelsforMulti-stageandSequentialCells,85
3.7.4 OtherNoiseModels...............................87
3.8 PowerDissipationModeling................................88
3.8.1 ActivePower ....................................88
DoubleCountingClockPinPower?,92
3.8.2 LeakagePower...................................92
3.9 OtherAttributesinCellLibrary .............................94
AreaSpecification,94
FunctionSpecification,95
SDFCondition,95
3.10 CharacterizationandOperatingConditions ....................96
WhatistheProcessVariable?,96
3.10.1 DeratingusingK-factors ...........................97
3.10.2 LibraryUnits ....................................99
CHAPTER 4: Interconnect Parasitics . . . . . . . . . . . . . . . . . . . . . 101
4.1 RLCforInterconnect ....................................102
T-model,103
Pi-model,104
4.2 WireloadModels........................................105
4.2.1 InterconnectTrees ...............................108
4.2.2 SpecifyingWireloadModels.......................110
4.3 RepresentationofExtractedParasitics .......................113
4.3.1 DetailedStandardParasiticFormat ..................113
4.3.2 ReducedStandardParasiticFormat..................115
4.3.3 StandardParasiticExchangeFormat.................117
4.4 RepresentingCouplingCapacitances........................118
4.5 HierarchicalMethodology ................................119
BlockReplicatedinLayout,120
4.6 ReducingParasiticsforCriticalNets ........................120
ReducingInterconnectResistance,120
IncreasingWireSpacing,121
vii
CONTENTS
ParasiticsforCorrelatedNets,121
CHAPTER 5: Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.1 Overview.............................................. 123
5.1.1 DelayCalculationBasics.......................... 123
5.1.2 DelayCalculationwithInterconnect................. 125
Pre-layoutTiming,125
Post-layoutTiming,126
5.2 CellDelayusingEffectiveCapacitance...................... 126
5.3 InterconnectDelay ...................................... 131
ElmoreDelay,132
HigherOrderInterconnectDelayEstimation,134
FullChipDelayCalculation,135
5.4 SlewMerging .......................................... 135
5.5 DifferentSlewThresholds ................................ 137
5.6 DifferentVoltageDomains................................ 140
5.7 PathDelayCalculation................................... 140
5.7.1 CombinationalPathDelay......................... 141
5.7.2 PathtoaFlip-flop ............................... 143
InputtoFlip-flopPath,143
Flip-floptoFlip-flopPath,144
5.7.3 MultiplePaths .................................. 145
5.8 SlackCalculation ....................................... 146
CHAPTER 6: Crosstalk and Noise . . . . . . . . . . . . . . . . . . . . . . . 147
6.1 Overview.............................................. 148
6.2 CrosstalkGlitchAnalysis................................. 150
6.2.1 Basics......................................... 150
6.2.2 TypesofGlitches................................ 152
RiseandFallGlitches,152
OvershootandUndershootGlitches,152
6.2.3 GlitchThresholdsandPropagation.................. 153
DCThresholds,153
ACThresholds,156
6.2.4 NoiseAccumulationwithMultipleAggressors......... 160
6.2.5 AggressorTimingCorrelation...................... 160
viii
CONTENTS
6.2.6 AggressorFunctionalCorrelation ...................162
6.3 CrosstalkDelayAnalysis .................................164
6.3.1 Basics.........................................164
6.3.2 PositiveandNegativeCrosstalk ....................167
6.3.3 AccumulationwithMultipleAggressors..............169
6.3.4 AggressorVictimTimingCorrelation................169
6.3.5 AggressorVictimFunctionalCorrelation .............171
6.4 TimingVerificationUsingCrosstalkDelay...................171
6.4.1 SetupAnalysis..................................172
6.4.2 HoldAnalysis...................................173
6.5 ComputationalComplexity................................175
HierarchicalDesignandAnalysis,175
FilteringofCouplingCapacitances,175
6.6 NoiseAvoidanceTechniques..............................176
CHAPTER 7: Configuringthe STA Environment . . . . . . . . . . . . 179
7.1 WhatistheSTAEnvironment? ............................180
7.2 SpecifyingClocks.......................................181
7.2.1 ClockUncertainty ...............................186
7.2.2 ClockLatency ..................................188
7.3 GeneratedClocks .......................................190
ExampleofMasterClockatClockGatingCellOutput,194
GeneratedClockusingEdgeandEdge_shiftOptions,195
GeneratedClockusingInvertOption,198
ClockLatencyforGeneratedClocks,200
TypicalClockGenerationScenario,200
7.4 ConstrainingInputPaths..................................201
7.5 ConstrainingOutputPaths ................................205
ExampleA,205
ExampleB,206
ExampleC,206
7.6 TimingPathGroups .....................................207
7.7 ModelingofExternalAttributes............................210
7.7.1 ModelingDriveStrengths .........................211
7.7.2 ModelingCapacitiveLoad.........................214
7.8 DesignRuleChecks .....................................215
ix
CONTENTS
7.9 VirtualClocks.......................................... 217
7.10 RefiningtheTimingAnalysis.............................. 219
7.10.1 SpecifyingInactiveSignals........................ 220
7.10.2 BreakingTimingArcsinCells ..................... 221
7.11 Point-to-PointSpecification ............................... 222
7.12 PathSegmentation ...................................... 224
CHAPTER 8: Timing Verification . . . . . . . . . . . . . . . . . . . . . . . . 227
8.1 SetupTimingCheck..................................... 228
8.1.1 Flip-floptoFlip-flopPath ......................... 231
8.1.2 InputtoFlip-flopPath............................ 237
InputPathwithActualClock,240
8.1.3 Flip-floptoOutputPath........................... 242
8.1.4 InputtoOutputPath.............................. 244
8.1.5 FrequencyHistogram............................. 246
8.2 HoldTimingCheck ..................................... 248
8.2.1 Flip-floptoFlip-flopPath ......................... 252
HoldSlackCalculation,253
8.2.2 InputtoFlip-flopPath............................ 254
8.2.3 Flip-floptoOutputPath........................... 256
Flip-floptoOutputPathwithActualClock,257
8.2.4 InputtoOutputPath.............................. 259
8.3 MulticyclePaths........................................ 260
CrossingClockDomains,266
8.4 FalsePaths ............................................ 272
8.5 Half-CyclePaths........................................ 274
8.6 RemovalTimingCheck .................................. 277
8.7 RecoveryTimingCheck.................................. 279
8.8 TimingacrossClockDomains ............................. 281
8.8.1 SlowtoFastClockDomains....................... 281
8.8.2 FasttoSlowClockDomains....................... 289
8.9 Examples.............................................. 295
Half-cyclePath-Case1,296
Half-cyclePath-Case2,298
FasttoSlowClockDomain,301
SlowtoFastClockDomain,303
x