Table Of ContentPARALLEL ALGORITHMS AND
ARCHITECTURES FOR DSP
APPLICATIONS
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PARALLEL ALGORITHMS AND
ARCHITECTURES FOR DSP
APPLICATIONS
Edited by
Magdy A. Bayoumi
The University ofS outhwestern Louisiana
~.
SPRINGER S"CIENC E+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
Parallel algorithms and architectures for DSP applications / edited by
Magdy A. Bayoumi.
p. cm. -- (The Kluwer international series in engineering and
computer science ; SECS 149. VLSI, computer architecture, and
digital signal processing)
Includes bibliographical references and index.
ISBN 978-1-4613-6786-4 ISBN 978-1-4615-3996-4 (eBook)
DOI 10.1007/978-1-4615-3996-4
1. Signal processing--Digital techniques. 2. Parallel processing
(Electronic computers) 3. Computer architectures. 4.lntegrated
circuits--Very large scale integration. 1. Bayoumi, Magdy A.
II. Series: Kluwer international series in engineering and computer
science ; SECS 149. III. Series: K1uwer international series in
engineering and computer science. kVLSI, computer architecture, and
digital signal procession.
TK5102.5.P352 1991
621.3822--dc20 91-26492
CIP
Copyright © 1991 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1991
Softcover reprint of the hardcover 1s t edition 1991
AlI rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmi tted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, Springer Science+
Busines Media, LLC
Printed on acid-free paper.
To the love of my life: Seham
Contents
Preface. ..................................................................................... ix
Chapter
1. Parallel Architectures for Iterative
Image Restoration
M. Sarrafzadeh, A. K. Katsaggelos and
S. P. R. Kumar. ........................................................... 1
2. Perfect Shuffle Communications in
Optically Interconnected Processor
Arrays
Z. Guo and R. G. Melhem ......................................... 33
3. Experiments with Parallel Fast Fourier
Transforms
G. Adams III, E. C. Bronson, T. L. Casavant,
L. H. J amieso1'l and R. A. Kamin III. ........................ .49
4. Fault-Tolerance for Parallel Adaptive
Beamforming
K. J. R. Liu and S. F. Hsieh ...................................... 77
5. Parallel Computation of Fan Beam
Back-Projection Reconstruction Algorithm
in Computed Tomography
Wen-Tai Lin, Chung-Yih Ho and
Chi-Yuan Chin .................................................... 113
viii
6. AfTme Permutations of Matrices on
Mesh-Connected Arrays
Bjorn Lisper and Sanjay Rajopadhye. ......................... 129
7. Architectures for Statically Scheduled
Dataflow
E. A. Lee and J. C. Bier. ............. ................................ 159
8. Design of Asynchronous Parallel
Architectures
Teresa H.-Y. Meng. .................................................... 191
9. Implementation of Multilayer Neural
Networks on Parallel Programmable
Digital Computers
S. Shams and K. W. Przytula ..................................... 225
10. Implementation of Sparse Neural
Networks on Fixed Size Arrays
M. Misra and V. K. Prasanna Kumar. ........................ 255
Index. ....................................................................................... 281
PREFACE
Over the past few years, the demand for high speed Digital Signal Proces-
sing (DSP) has increased dramatically. New applications in real-time image
processing, satellite communications, radar signal processing, pattern recogni-
tion, and real-time signal detection and estimation require major improvements
at several levels; algorithmic, architectural, and implementation. These perfor-
mance requirements can be achieved by employing parallel processing at all
levels. Very Large Scale Integration (VLSI) technology supports and provides
a good avenue for parallelism.
Parallelism offers efficient sohitions to several problems which can arise in
VLSI DSP architectures such as:
1. Intermediate data communication and routing: several DSP algorithms,
such as FFT, involve excessive data routing and reordering. Parallelism is
an efficient mechanism to minimize the silicon cost and speed up the pro-
cessing time of the intermediate middle stages.
2. Complex DSP applications: the required computation is almost doubled.
Parallelism will allow two similar channels processing at the same time.
The communication between the two channels has to be minimized.
3. Applicatilm specific systems: this emerging approach should achieve real-time
performance in a cost-effective way.
4. Testability and fault tolerance: reliability has become a required feature in
most of DSP systems. To achieve such property, the involved time
overhead is significant. Parallelism may be the solution to maintain ac-
ceptable speed performance.
Parallelism can be achieved at different levels; algorithms, architectures,
and implementation. Most DSP algorithms have inherent parallelism in com-
putation steps and data manipulation. The architecture band extends across
different classes of parallelism; (1) using a set of Von Neuman processors and
one or more shared memories, (2) achieving concurrency by employing an
asynchronous timing paradigm, (3) large grain computation on a few powerful
x
processors (such as Intel iPSq, (4) fine-grain computation on many simple
processors (such as the Connection Machine), or (5) VLSI arrays which have re-
gular and local communication, local control and I/O restricted boundaries.
In achieving parallelism, several problems will arise which need to be tackled.
This book addresses several related issues and problems focussed on DSP
algorithms and architectures. The main topics which have been discussed in this
book are:
• CommunicRtion: This problem ranges from global but not very scalable solu-
tions, like busses, through somewhat more scalable solutions like interconnec-
tion networks, to local but scalable point-to-point connection schemes. Several
solutions have been offered which are DSP applications dependent; VLSI arrays
for matrix-based computations (Chapter 6), mesh, pyramid, and combinations
between them (Chapter 1), Orthogonal trees (Chapter 5).
• Emerging Technologies: Optical communication has been investigated with a
case study of shuflle-exchange topology (Chapter 2). Neural Network (NN)
technology provides a new paradigm for parallelism. Implementing NN on
parallel architectures is an essential step to achieve the expected performance.
Two case studies have been discussed; (1) Mapping multilayer perceptron NN
onto SIMD arrays with achieving high throughput and flexibility (Chapter 9),
and (2) mapping general NN onto fixed size array taking into consideration the
used learning model (Chapter 10).
• Design Environments Rnd ExperimentRtion: With the increasing complexity of
implemented systems, design environments, frameworks and simulation have
become necessary design tools. Two examples have been given; one for asyn-
chronous systems (Chapter 8) and another for shared memory architectures
(Chapter 7). Analyzing the performance of an algorithm running on specific
architectures can be used as guidelines for algorithm evaluation and implemen-
tation. As a case study, Fast Fourier Transform (FFT) algorithm has been
analyzed using the Connection Machine and the PASM computer (a research
computer at Purdue University) (Chapter 3).
• ApplicRtions: Three intensive computation case studies have been addressed;
(1) Back-Projection Reconstruction (BPR) for Computer Tomography,
(Chapter 5), (2) Adaptive Beamforming for Spatial Filtering > From an Array
of Sensors (Chapter 4), and (3) Iterative Image Restoration (Chapter 1).
• Algorithm Design: The central point is to take advantage of the substantial
parallelism of DSP algorithms and to obtain the maximum performance from
complex parallel architectures. Parallelism on the algorithmic level can be em-
ployed for fault-tolerance (Chapter 4). Devising mapping methodologies for al-
gorithms onto parallel architectures is gaining considerable interest; an example
of mapping matrix-based computation on VLSI arrays is discussed (Chapter 6).
These mapping methodologies are evaluated based on the implementation tech-
nology. In VLSI, AT2 can be used as a performance measure (Chapter 1).
xi
The intent of this book is to be informative and stimulating for the
readers to gain knowledge and participate in fast evolving VLSI DSP field. It
establishes a good understanding of the strength of parallel DSP in different ap-
plications and on various architectures. The book can be used as a textbook for
research courses in VLSI, DSP, Parallel Processing, and DSP Architectures. It
can be used as a supplementary text for graduate and senior undergraduate
courses in VLSI Architecture and design for DSP applications. It can also serve
as a material for tutorials and short courses in VLSI DSP Architectures, DSP
systems design and Parallel Processing.
The idea of this book was motivated by a special session with the same
title "Parallel Algorithms and Architectures for DSP Applications" at IS CAS
1990 in New Orleans. That session was sponsored by the VLSI Systems and
Applications (VSA) Technical Committee of the Circuits and Systems Society.
I extend thanks to the members of this committee and to the speakers of that
session for supporting the idea of this book when it was in its infancy stage.
My sincere appreciation to the VLSI Signal Processing Technical Committee of
the ASSP society which provides a stimulating environment and a constructive
infrastructure for VLSI Signal Processing activities. Special thanks to the au-
thors who patiently spent considerable time and effort to have their research
work reported in this book. It has been a stimulating and constructive ex-
perience working with such a group of highly motivated scholars. The environ-
ment in the Center for Advanced Computer Studies has been dynamic, inspi-
ring and supportive for such project. My sincere thanks to Kluwer Academic
Publishers for the enthusiasm they showed about this book, to Bob Holland,
the editor and his assistant Rose Luongo for their support, encouragement, and
patience. They have established a friendly communication channel for me.
Finally, I would like to acknowledge my lovely wife, Seham, and my in-
teresting children; Aiman, Walid, and Amanda for their support and sacrifice
during the course of this project. Seham does not believe that I finished my stu-
dies yet because of my working at night and during the weekends. I appreciate
that she allows me to use our dining table as a desk because my office at home
is ultra crowded. My younger son, Walid, always calls me Dr. Magdy Bay-
oumi, to remind my wife.
Magdy Bayoumi
