Microprocessor architecture : from simple pipelines to chip multiprocessors

384 Pages·2010·13.072 MB·English

by  Jean-Loup Baer

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MICROPROCESSOR ARCHITECTURE
This book gives a comprehensive description of the architecture of
microprocessorsfromsimplein-ordershortpipelinedesignstoout-of-
ordersuperscalars.Itdiscussestopicssuchas
(cid:1)
Thepoliciesandmechanismsneededforout-of-orderprocessing,
suchasregisterrenaming,reservationstations,andreorderbuffers
(cid:1)
Optimizations for high performance, such as branch predictors,
instructionscheduling,andload–storespeculations
(cid:1)
Designchoicesandenhancementstotoleratelatencyinthecache
hierarchyofsingleandmultipleprocessors
(cid:1)
State-of-the-artmultithreadingandmultiprocessing,emphasizing
single-chipimplementations
Topics are presented as conceptual ideas, with metrics to assess the
effects on performance, if appropriate, and examples of realization.
The emphasis is on how things work at a black box and algorithmic
level. The author also provides sufficient detail at the register trans-
fer level so that readers can appreciate how design features enhance
performanceaswellascomplexity.
Jean-LoupBaerisProfessorEmeritusofComputerScienceandEngi-
neeringattheUniversityofWashington,wherehehasbeensince1969.
ProfessorBaeristheauthorofComputerSystemsArchitectureandof
morethan100refereedpapers.HeisaGuggenheimFellow,anACM
Fellow,andanIEEEFellow.Baerhasheldseveraleditorialpositions,
includingeditor-in-chiefoftheJournalofVLSIandComputerSystems
andeditoroftheIEEETransactionsonComputers,theIEEETrans-
actionsonParallelandDistributedSystems,andtheJournalofParallel
andDistributedComputing.HehasservedasGeneralChairandPro-
gramChairofseveralconferences,includingISCAandHPCA.

Microprocessor Architecture
FROM SIMPLE PIPELINES TO CHIP
MULTIPROCESSORS
Jean-Loup Baer
UniversityofWashington,Seattle
CAMBRIDGEUNIVERSITYPRESS
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Cambridge University Press
The Edinburgh Building, Cambridge CB2 8RU, UK
Published in the United States of America by Cambridge University Press, New York
www.cambridge.org
Information on this title: www.cambridge.org/9780521769921
© Jean-Loup Baer 2010
This publication is in copyright. Subject to statutory exception and to the
provision of relevant collective licensing agreements, no reproduction of any part
may take place without the written permission of Cambridge University Press.
First published in print format 2010
ISBN-13 978-0-511-67546-1 eBook (NetLibrary)
ISBN-13 978-0-521-76992-1 Hardback
Cambridge University Press has no responsibility for the persistence or accuracy
of urls for external or third-party internet websites referred to in this publication,
and does not guarantee that any content on such websites is, or will remain,
accurate or appropriate.
ToDiane,Marc,Shawn,andDanielle

Contents
Preface pagexi
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 AQuickViewofTechnologicalAdvances 2
1.2 PerformanceMetrics 6
1.3 PerformanceEvaluation 12
1.4 Summary 22
1.5 FurtherReadingandBibliographicalNotes 23
exercises 24
references 28
2 TheBasics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1 Pipelining 29
2.2 Caches 46
2.3 VirtualMemoryandPaging 59
2.4 Summary 68
2.5 FurtherReadingandBibliographicalNotes 68
exercises 69
references 73
3 SuperscalarProcessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.1 FromScalartoSuperscalarProcessors 75
3.2 OverviewoftheInstructionPipelineoftheDECAlpha21164 78
3.3 IntroducingRegisterRenaming,ReorderBuffer,and
ReservationStations 89
3.4 OverviewofthePentiumP6Microarchitecture 102
3.5 VLIW/EPICProcessors 111
3.6 Summary 121
3.7 FurtherReadingandBibliographicalNotes 122
exercises 124
references 126
vii
viii Contents
4 Front-End:BranchPrediction,InstructionFetching,andRegister
Renaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.1 BranchPrediction 130
Sidebar:TheDECAlpha21264BranchPredictor 157
4.2 InstructionFetching 158
4.3 Decoding 164
4.4 RegisterRenaming(aSecondLook) 165
4.5 Summary 170
4.6 FurtherReadingandBibliographicalNotes 170
exercises 171
ProgrammingProjects 174
references 174
5 Back-End:InstructionScheduling,MemoryAccessInstructions,
andClusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
5.1 InstructionIssueandScheduling(WakeupandSelect) 178
5.2 Memory-AccessingInstructions 184
5.3 Back-EndOptimizations 195
5.4 Summary 203
5.5 FurtherReadingandBibliographicalNotes 204
exercises 205
ProgrammingProject 206
references 206
6 TheCacheHierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.1 ImprovingAccesstoL1Caches 209
6.2 HidingMemoryLatencies 218
6.3 DesignIssuesforLargeHigher-LevelCaches 232
6.4 MainMemory 245
6.5 Summary 253
6.6 FurtherReadingandBibliographicalNotes 254
exercises 255
ProgrammingProjects 257
references 258
7 Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
7.1 MultiprocessorOrganization 261
7.2 CacheCoherence 269
7.3 Synchronization 281
7.4 RelaxedMemoryModels 290
7.5 MultimediaInstructionSetExtensions 294
7.6 Summary 296
7.7 FurtherReadingandBibliographicalNotes 297
exercises 298
references 300