Computer Organization, Design, and Architecture, Fourth Edition

769 Pages·2007·10.18 MB·English

by  Sajjan G. Shiva

Computer Organization,
Design, and Architecture
Fourth Edition
(cid:1)2007byTaylor&FrancisGroup,LLC.
(cid:1)2007byTaylor&FrancisGroup,LLC.
Computer Organization,
Design, and Architecture
Fourth Edition
Sajjan G. Shiva
Boca Raton London New York
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
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Library of Congress Cataloging-in-Publication Data
Shiva, Sajjan G.
Computer organization, design, and architecture / Sajjan G. Shiva. -- 4th ed.
p. cm.
Previously published: New York : Marcel Dekker, 3rd ed., rev. and expanded, under title:
Computer design and architecture, 2000.
Includes bibliographical references and index.
ISBN-13: 978-0-8493-0416-3
ISBN-10: 0-8493-0416-4
1. Computer engineering. 2. Computer architecture. I. Shiva, Sajjan G. Computer design
and architecture. II. Title.
TK7885.S525 2008
621.39--dc22 2007020766
Visit the Taylor & Francis Web site at
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(cid:1)2007byTaylor&FrancisGroup,LLC.
To
my parents
(cid:1)2007byTaylor&FrancisGroup,LLC.
(cid:1)2007byTaylor&FrancisGroup,LLC.
Contents
Preface
Chapter 1 Introduction
1.1 ComputerSystem Organization
1.1.1 Hardware
1.1.2 Software
1.1.3 System
1.2 ComputerEvolution
1.2.1 Von Neumann Model
1.2.2 Generations ofComputerTechnology
1.2.3 Moore’s Law
1.3 Organization versusDesignversus Architecture
1.4 Performance Evaluation
1.4.1 Benchmarks
1.5 Summary
References
Problems
Chapter 2 Number Systems andCodes
2.1 Number Systems
2.1.1 BinarySystem
2.1.2 Octal System
2.1.3 Hexadecimal System
2.2 Conversion
2.2.1 Radix Divide Technique
2.2.2 Radix Multiply Technique
k
2.2.3 Base 2 Conversion
2.3 Arithmetic
2.3.1 BinaryArithmetic
2.3.1.1 Addition
2.3.1.2 Subtraction
2.3.1.3 Multiplication
2.3.1.4 Division
2.3.1.5 Shifting
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2.3.2 Octal Arithmetic
2.3.3 Hexadecimal Arithmetic
2.4 Sign-Magnitude System
2.5 Complement Number System
2.5.1 2sComplement Addition
2.5.2 1sComplement Addition
2.5.3 Shifting Revisited
2.5.4 Comparisonof Complement Systems
2.6 Floating-PointNumbers
2.6.1 IEEE Standard
2.6.1.1 Single Precision
2.6.1.2 Double Precision
2.6.1.3 Comparison
2.6.1.4 Rounding
2.6.1.5 Accuracy
2.6.1.6 Exceptions
2.7 Binary Codes
2.7.1 WeightedCodes
2.7.2 NonweightedCodes
2.7.3 Error-Detection Codes
2.7.4 Alphanumeric Codes
2.8 Data Storage and Register Transfer
2.9 Representationof Numbers,Arrays, andRecords
2.9.1 BCD Numbers
2.9.2 Floating-PointNumbers
2.9.3 Representation ofStrings
2.9.4 Arrays
2.9.5 Records
2.10 Summary
References
Problems
Chapter3 CombinationalLogic
3.1 Basic Operationsand Terminology
3.1.1 Evaluation of Expressions
3.1.2 Truth Tables
3.1.3 Functions andTheir Representation
3.1.4 Canonical Forms
3.2 Boolean Algebra(Switching Algebra)
3.3 Minimizationof Boolean Functions
3.3.1 Venn Diagrams
3.3.2 Karnaugh Maps
3.3.3 Quine–McCluskey Procedure
3.4 Primitive Hardware Blocks
3.5 FunctionalAnalysisofCombinationalCircuits
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3.6 Synthesis ofCombinational Circuits
3.6.1 AND–OR Circuits
3.6.2 OR–AND Circuits
3.6.3 NAND–NANDand NOR–NOR Circuits
3.7 Some PopularCombinationalCircuits
3.7.1 Adders
3.7.2 Decoders
3.7.3 CodeConverters
3.7.4 Encoders
3.7.5 Multiplexers
3.7.6 Demultiplexers
3.8 Integrated Circuits
3.8.1 Positiveand Negative Logic
3.8.2 SignalInversion
3.8.3 Other Characteristics
3.8.4 Special Outputs
3.8.5 Designingwith ICs
3.9 Loadingand Timing
3.10 Summary
References
Problems
Chapter 4 SynchronousSequentialCircuits
4.1 Flip-Flops
4.1.1 Set–Reset Flip-Flop
4.1.2 DFlip-Flop
4.1.3 JK Flip-Flop
4.1.4 T Flip-Flop
4.1.5 Characteristic and ExcitationTables
4.2 Timing Characteristics of Flip-Flops
4.2.1 Master–SlaveFlip-Flops
4.2.2 Edge-Triggered Flip-Flops
4.3 Flip-FlopICs
4.4 AnalysisofSynchronous SequentialCircuits
4.5 Design ofSynchronous Sequential Circuits
4.6 Registers
4.7 RegisterTransfer Logic
4.8 RegisterTransfer Schemes
4.8.1 Point-to-Point Transfer
4.8.2 Bus Transfer
4.9 RegisterTransfer Languages
4.10 DesigningSequentialCircuitswithIntegrated Circuits
4.11 Programmable Logic
4.11.1 CircuitImplementation Modes and Devices
4.11.2 Programmable Logic Arrays
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