19-5309; Rev 0; 6/10 EVAALVUAAILTAIOBNL EKIT Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs M General Description Features The MAX19527 is an octal, 12-bit analog-to-digital S Ultra-Low-Power Operation A converter (ADC), optimized for the low-power and 55mW per Channel at 50Msps X high-dynamic performance requirements of medical S Single 1.8V Power Supply 1 imaging instrumentation and digital communications S Excellent Dynamic Performance 9 applications. The device operates from a single 1.8V 69dBFS SNR at 5.3MHz 5 supply and consumes 440mW (55mW per channel), while providing a 69dBFS signal-to-noise ratio (SNR) at 140dBc/Hz Near-Carrier SNR at 1kHz Offset 2 a 5.3MHz input frequency. In addition to low operating from a 5.3MHz Tone 7 84dBc SFDR at 5.3MHz power, the device features programmable power man- 90dB Channel Isolation at 5.3MHz agement for idle states and reduced-channel operation. S User-Programmable Adjustment and Feature An internal 1.25V precision bandgap reference sets the Selection through an SPI Interface full-scale range of the ADC to 1.5VP-P. A flexible reference structure allows the use of an external reference S Serial LVDS Outputs with Programmable Current for applications requiring greater gain accuracy or a Drive and Internal Termination different input voltage range. A programmable common- S Programmable Power Management mode voltage reference output is provided to enable S Internal or External Reference Operation DC-coupled input applications. S Single-Ended or Differential Clock Input Various adjustments and feature selections are available through programmable registers that are accessed S Programmable Output Data Format through the 3-wire serial peripheral interface (SPIK). S Built-In Output Data Test Patterns A flexible clock input circuit allows for a single-ended, S Small, 10mm x 10mm, 144-Lead CTBGA Package logic-level clock or a differential clock signal. An on-chip S Evaluation Kit Available (Order MAX19527EVKIT+) PLL generates the multiplied (6x) clock required for the serial LVDS digital outputs. The serial LVDS output provides programmable test patterns for data timing alignment and output drivers with programmable current drive and programmable internal termination. The device is available in a small, 10mm x 10mm x 1.2mm, 144-lead thin chip ball grid array (CTBGA) package and is specified for the extended industrial (-40NC to +85NC) temperature range. Applications Ordering Information Ultrasound and Medical Imaging PART TEMP RANGE PIN-PACKAGE Instrumentation MAX19527EXE+ -40NC to +85NC 144 CTBGA Multichannel Communications +Denotes a lead(Pb)-free/RoHS-compliant package. ZIF GSM and TD-SCDMA Transceivers SPI is a trademark of Motorola, Inc. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 7 ABSOLUTE MAXIMUM RATINGS 2 AVDD, OVDD to GND ......................................... -0.3V to +2.1V Continuous Power Dissipation (TA = +70NC) 5 OGND to GND ......................................................-0.3V to +0.3V 144-Lead CTBGA (derate 37mW/NC above +70NC) 9 IN_+, IN_-, CMOUT, REFIO, REFH, Multilayer Board ...................................................... 2963mW 1 REFL, CLKIN+, CLKIN- to GND ..............-0.3V to the lower of Operating Temperature Range .........................-40NC to +85NC X (VAVDD + 0.3V) and +2.1V Junction Temperature ....................................................+150NC OUT_+, OUT_-, FRAME+, Storage Temperature Range ..........................-65NC to +150NC A FRAME-, CLKOUT+, CLKOUT-, Lead Temperature (soldering, 10s) ................................+300NC M SHDN, CS, SCLK, SDIO to GND .............-0.3V to the lower of Soldering Temperature (reflow) ......................................+260NC (VOVDD + 0.3V) and +2.1V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 12 Bits Integral Nonlinearity INL fIN = 5.3MHz Q0.5 Q1.7 LSB Differential Nonlinearity DNL fIN = 5.3MHz, no missing codes Q0.3 Q1.0 LSB Offset Error OE Internal reference Q0.07 Q0.7 %FS Gain Error GE External reference = 1.25V Q0.2 Q3.0 %FS ANALOG INPUTS (IN_+, IN_-) (Figure 2) Input Differential Range VDIFF IN_+ - IN_- 1.5 VP-P Common-Mode Input Voltage VCM Q50mV tolerance 1050 mV Range Fixed resistance to GND > 100 Input Resistance RIN Differential input resistance, common kI 4 mode connected to inputs Switched capacitance input current, Input Current IIN 36 FA each input, VCM = 1.050V CINS Fixed capacitance to GND, each input 1 Input Capacitance CIND Fixed differential capacitance 0.2 pF CSAMPLE Switched capacitance, each input 1.5 CONVERSION RATE Maximum Clock Frequency fCLK 50 MHz Minimum Clock Frequency fCLK 25 MHz Clock Data Latency Figure 5 8.5 Cycles 2 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) M (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable A registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 DYNAMIC PERFORMANCE 9 Small-Signal Noise Floor SSNF Analog input < -35dBFS, fIN = 5.3MHz -69.5 dBFS 5 1kHz offset from 5.3MHz full-scale tone, 2 Near-Carrier Signal-to-Noise CREFIO = CREFH/REFL = 0.1FF 140 NCSNR dBc/Hz 7 Ratio (Figure 3) 8-channel coherent sum 147 fIN = 5.3MHz at -0.5dBFS 67.0 68.5 Signal-to-Noise Ratio SNR dB fIN = 19.3MHz at -0.5dBFS 68.5 Signal-to-Noise and Distortion fIN = 5.3MHz at -0.5dBFS 66.6 68.2 SINAD dB Ratio fIN = 19.3MHz at -0.5dBFS 68.2 fIN = 5.3MHz at -0.5dBFS 70.0 84 Spurious-Free Dynamic Range SFDR dBc fIN = 19.3MHz at -0.5dBFS 84 fIN = 5.3MHz at -0.5dBFS -81 -72 Total Harmonic Distortion THD dBc fIN = 19.3MHz at -0.5dBFS -81 fIN1 = 5.15MHz at -6.5dBFS, Intermodulation Distortion IMD -83 dB fIN2 = 5.45MHz at -6.5dBFS Full-Power Bandwidth FPBW RSOURCE = 50I differential > 500 MHz 6dB beyond full scale (recover accuracy Clock Overdrive Recovery Time < 1 to < 1% of full scale) Cycles INTERCHANNEL CHARACTERISTICS Crosstalk fIN = 5.3MHz at -0.5dBFS -90 dB Gain Matching fIN = 5.3MHz Q0.1 dB Phase Matching fIN = 5.3MHz Q0.25 Degrees ANALOG OUTPUT (CMOUT) CMOUT Output Voltage VCMOUT Default programming state 1.05 1.10 1.15 V INTERNAL REFERENCE REFIO Output Voltage VREFIO Bypass only, no DC load 1.22 1.25 1.28 V REFIO Temperature Coefficient TCREF < Q60 ppm/NC REFH Voltage VREFH Bypass only, no DC load 1.61 V REFL Voltage VREFL Bypass only, no DC load 0.86 V EXTERNAL REFERENCE REFIO Input Voltage Range VREFIN +5%/-15% tolerance 1.25 V REFIO Input Resistance RREFIN 10 Q 20% kI 3 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 7 ELECTRICAL CHARACTERISTICS (continued) 2 (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable 5 registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1) 9 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 CLOCK INPUTS (CLKIN+, CLKIN-)—DIFFERENTIAL MODE (Figure 4) X Differential Clock Input Voltage VCLKD 0.4 to 2.0 VP-P A Self-biased 1.2 M Common-Mode Voltage VCLKCM DC-coupled clock signal 1.0 to 1.4 V Differential, default setting 10 Differential, programmable internal Input Resistance RCLK 0.1 kI termination selected Common mode to GND 9 Input Capacitance CCLK Capacitance to GND, each input 3 pF CLOCK INPUTS (CLKIN+, CLKIN-)—SINGLE-ENDED MODE (CLKIN- < 0.1V) (Figure 4) Single-Ended Mode Selection VIL 0.1 V Threshold (CLKIN-) Single-Ended Clock Input High VIH 1.5 V Threshold (CLKIN+) Single-Ended Clock Input Low VIL 0.3 V Threshold (CLKIN+) IIH VIH = 1.8V +5 Input Leakage (CLKIN+) FA IIL VIH = 0V -5 Input Leakage (CLKIN-) IIL VIH = 0V -150 -50 FA Input Capacitance (CLKIN+) 3 pF DIGITAL INPUTS (SHDN, SCLK, SDIN, CS) Input High Threshold VIH 1.5 V Input Low Threshold VIL 0.3 V IIH VIH = 1.8V +5 Input Leakage FA IIL VIL = 0V -5 Input Capacitance CDIN 3 pF DIGITAL OUTPUTS (SDIO) Output Voltage Low VOL ISINK = 200FA 0.2 V OVDD - Output Voltage High VOH ISOURCE = 200FA V 0.2 LVDS DIGITAL OUTPUTS (OUT_+/OUT_-, CLKOUT+/CLKOUT-, FRAME+/FRAME-) Differential Output Voltage |VOD| External RLOAD = 100I 250 450 mV Output Offset Voltage VOS External RLOAD = 100I 1.125 1.375 V POWER-MANAGEMENT CHARACTERISTICS (Figure 3) Internal reference, CREFIO = 0.1FF, Wake-Up Time from Sleep Mode tSWAKE CREFH/REFL = 0.1FF; Q1% gain error, 10 ms with respect to steady-state gain Internal reference, CREFIO = 0.1FF, Wake-Up Time from Nap Mode tNWAKE CREFH/REFL = 0.1FF; Q1% gain error, 2 Fs with respect to steady-state gain 4 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs ELECTRICAL CHARACTERISTICS (continued) M (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable A registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted.) (Note 1) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9, Note 2) 9 SCLK Period tSCLK 50 ns 5 SCLK to CS Setup Time tCSS 10 ns 2 SCLK to CS Hold Time tCSH 10 ns 7 SDIO to SCLK Setup Time tSDS Serial-data write 10 ns SDIO to SCLK Hold Time tSDH Serial-data write 0 ns SCLK to SDIO Output Data Delay tSDD Serial-data read 10 ns TIMING CHARACTERISTICS (Figures 6 and 7, Note 2) tSAMPLE/ tSAMPLE/ tSAMPLE/ Data Valid to CLKOUT Rise/Fall tOD ns 24 - 0.10 24 + 0.05 24 + 0.20 CLKOUT Output-Width High tCH tSAMPLE/12 ns CLKOUT Output-Width Low tCL tSAMPLE/12 ns tSAMPLE/ tSAMPLE/ tSAMPLE/ FRAME Rise to CLKOUT Rise tDF ns 24 - 0.10 24 + 0.05 24 + 0.20 tSAMPLE/ tSAMPLE/ tSAMPLE/ Sample CLK Rise to Frame Rise tSF ns 2 + 1.6 2 + 2.3 2 + 3.3 POWER REQUIREMENTS Analog Supply Voltage VAVDD 1.7 1.8 1.9 V Digital Output Supply Voltage VOVDD 1.7 1.8 1.9 V 8 channels active 158 180 Incremental channel power-down -18 Analog Supply Current IAVDD mA Nap mode 13 15 Sleep mode 0.35 0.5 8 channels active, external RLOAD = 100I 87 Incremental channel power-down -7.4 Digital Output Supply Current IOVDD mA Nap mode 28 Sleep mode < 0.1 8 channels active 440 Incremental channel power-down -46 Total Power Dissipation PTD mW Nap mode 74 Sleep mode 0.8 Note 1: Specifications are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization. Note 2: Specifications guaranteed by design and characterization. 5 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 7 Typical Operating Characteristics 2 5 (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications 9 are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.) 1 X 5.3MHz INPUT FFT PLOT 19.3MHz INPUT FFT PLOT CROSSTALK FFT PLOT 0 0 0 MA --2100 fIN A=SI N5N .=R3 0 -=01 .3642894.d5MB8FdHSBz MAX19527 toc01 --2100 fASININN R= = 1= -9 06..3850.143d99Bd0FB0SMHz MAX19527 toc02 --2100 MWEIATHSU INRTEEDR OFONENR C ICNHHGAA NSNNINGEENLLA 1 L2, MAX19527 toc03 -30 SINAD = 68.35dB -30 SINAD = 68.24dB -30 fIN(IN1) = 5.301324MHz dBFS) -40 TSHFDD =R -=8 815.1.197ddBBc dBFS) -40 TSHFDDR = =- 8805..9703ddBBc dBFS) -40 fIN(INA2)I N=( I1N91.)3 =0 3-09.050dMBFHSz DE ( -50 DE ( -50 DE ( -50 AIN(IN2) = -0.5dBFS TU -60 TU -60 TU -60 CROSSTALK = -92dB LI LI LI P P P M -70 M -70 M -70 A A A -80 -80 -80 fIN(IN2) = 19.3039MHz -90 -90 -90 -100 -100 -100 -110 -110 -110 0 5 10 15 20 25 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) TWO-TONE INTERMODULATION 5.3MHz INPUT FFT PLOT INTEGRAL NONLINEARITY DISTORTION 8-CHANNEL COHERENT SUM vs. DIGITAL OUTPUT CODE PLITUDE (dBFS) ------6543210000000 ffIINN12AA II==NN 1255I M..==14 352--67 43=..8490 -2052884dd3MMBBdFFBHHSSczz MAX19527 toc04 PLITUDE (dBFS) -------765432100000000 fINSTS AIH=NSFI ND5NAD .=D=RR3 0 --===018 .3778752769.084...d2830MB041dFdddBHSBBBcz MAX19527 toc05 INL (LSB) -000001......0224680 MAX19527 toc06 M -70 M A A -80 -0.4 -80 -90 -90 -100 -0.6 -100 -110 -0.8 -110 -120 -1.0 0 5 10 15 20 25 0 5 10 15 20 25 0 512 1024 1536 2048 2560 3072 3584 4096 FREQUENCY (MHz) FREQUENCY (MHz) DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE vs. DIGITAL OUTPUT CODE vs. INPUT FREQUENCY vs. ANALOG INPUT POWER 1.0 90 90 000...468 MAX19527 toc07 NCE (dB) 8805 SFDR MAX195027 toc08 NCE (dB) 7800 -THD SFDR MAX19527 toc09 B) 0.2 MA MA 60 S R R NL (L 0 ERFO 75 -THD ERFO 50 SNR D -0.2 C P SNR C P 40 -0.4 AMI 70 AMI SINAD YN YN 30 -0.6 D D 65 -0.8 SINAD 20 -1.0 60 10 0 512 1024 1536 2048 2560 3072 3584 4096 0 50 100 150 200 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 DIGITAL OUTPUT CODE INPUT FREQUENCY (MHz) ANALOG INPUT POWER (dBFS) 6 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs Typical Operating Characteristics (continued) M (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable A registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications X are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.) 1 DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE 9 vs. SAMPLING RATE vs. INPUT COMMON-MODE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 5 MIC PERFORMANCE (dB) 7788905050 -THDSSFNDRR MAX19527 toc10 MIC PERFORMANCE (dB) 7788905050 -THD SSFNDRR MAX19527 toc11 MIC PERFORMANCE (dB) 7788905050 -THDSSFNDRR MAX19527 toc12 27 DYNA DYNA DYNA 65 SINAD 65 SINAD 65 SINAD 60 60 60 25 30 35 40 45 50 0.95 1.00 1.05 1.10 1.15 1.65 1.70 1.75 1.80 1.85 1.90 1.95 SAMPLING RATE (MHz) INPUT COMMON-MODE VOLTAGE (V) VAVDD (V) DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE NEAR-CARRIER NOISE SPECTRUM vs. CLOCK DUTY CYCLE vs. TEMPERATURE vs. FREQUENCY OFFSET 90 90 -120 MANCE (dB) 8805 -THD SFDR MAX19527 toc13 MANCE (dB) 8805 SFDR MAX19527 toc14 ECTRUM (dBC/Hz)-130 CSHIANNGNLEEL MAX19527 toc15 RFOR 75 RFOR 75 -THD SE SP-140 MIC PE 70 SNR MIC PE 70 SNR ER NOI YNA YNA ARRI-150 D D C 65 SINAD 65 SINAD AR- 8-CHANNEL E SINGLE-ENDED CLOCK MODE N COHERENT SUM 60 60 -160 30 35 40 45 50 55 60 65 70 -40 -15 10 35 60 85 -5 -3 -1 1 3 5 CLOCK DUTY CYCLE (%) TEMPERATURE (°C) FREQUENCY OFFSET (kHz) +6dB OVERDRIVE +6dB OVERDRIVE ANALOG SUPPLY CURRENT OUTPUT CODE vs. SIGNAL PHASE ERROR vs. SIGNAL PHASE vs. SAMPLING RATE (AVDD) 4096 1.00 180 +6dB OVERDRIVE OUTPUT CODE112323050055234768468204 CLIP4P09E5D AT CALfIIINNP =P= E+5D6.3 dAMBTFHSz MAX19527 toc16 +6dB OVERDRIVE ERROR (LSB) --00000.....52527005055 CLIP4P09E5D AT CALfIIINNP =P=0 E+5D6.3 dAMBTFHSz MAX19527 toc17 ANALOG SUPPLY CURRENT (mA) 111146802460000000 1 CHANNEL7 C8H CAHNANNE4NL CSEHLSANNELS MAX19527 toc18 0 512 -0.75 20 NAP MODE 0 -1.00 0 0 60 120 180 240 300 360 0 60 120 180 240 300 360 25 30 35 40 45 50 SIGNAL PHASE (DEGREES) SIGNAL PHASE (DEGREES) SAMPLING RATE (MHz) 7 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 7 Typical Operating Characteristics (continued) 2 (VAVDD = 1.8V, VOVDD = 1.8V, internal reference, AIN = -0.5dBFS, differential clock, VCLKD = 1.5VP-P, fCLK = 50MHz, programmable 5 registers at default settings (Table 1), TA = -40NC to +85NC, typical values are at TA = +25NC, unless otherwise noted. Specifications 9 are 100% production tested at TA R +25NC. Specifications for TA < +25NC are guaranteed by design and characterization.) 1 ANALOG SUPPLY CURRENT ANALOG SUPPLY CURRENT DIGITAL SUPPLY CURRENT X vs. TEMPERATURE (AVDD) vs. SUPPLY VOLTAGE (AVDD) vs. SAMPLING RATE (OVDD) 180 170 100 MA mA) 175 MAX19527 toc19 mA) 165 MAX19527 toc20 mA) 8900 8 CHANNELS MAX19527 toc21 URRENT ( 117605 URRENT ( 160 URRENT ( 6700 7 CHANNELS C C C OG SUPPLY 115650 OG SUPPLY 115505 AL SUPPLY 345000 4 CHAN1N CELHSANNEL ANAL 150 ANAL 145 DIGIT 20 NAP MODE 145 10 140 140 0 -40 -15 10 35 60 85 1.65 1.70 1.75 1.80 1.85 1.90 1.95 25 30 35 40 45 50 TEMPERATURE (°C) SUPPLY VOLTAGE (V) SAMPLING RATE (MHz) DIGITAL SUPPLY CURRENT DIGITAL SUPPLY CURRENT REFERENCE VOLTAGE vs. TEMPERATURE (OVDD) vs. SUPPLY VOLTAGE (OVDD) vs. TEMPERATURE 95 100 1.260 mA) MAX19527 toc22 mA) 95 MAX19527 toc23 1.255 MAX19527 toc24 DIGITAL SUPPLY CURRENT ( 889050 DIGITAL SUPPLY CURRENT ( 78895050 REFERENCE VOLTAGE (V)111...222445050 75 70 1.230 -40 -15 10 35 60 85 1.65 1.70 1.75 1.80 1.85 1.90 1.95 -40 -15 10 35 60 85 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) ANALOG INPUT CURRENT CMOUT VOLTAGE CMOUT VOLTAGE vs. INPUT COMMON-MODE vs. TEMPERATURE vs. CMOUT LOAD CURRENT VOLTAGE (AVDD) 111...111468 111110 CMI_ADJ[2:0] MAX19527 toc25 11..1112 MAX19527 toc26 A) 4550 MAX19527 toc27 µ LTAGE (V) 11..1102 110010 LTAGE (V) 1.10 CURRENT ( 40 T VO 1.08 011 T VO PUT 35 CMOU 1.06 010 CMOU 1.09 LOG IN 30 001 A 1.04 1.08 AN 000 25 1.02 1.00 1.07 20 -40 -20 0 20 40 60 80 0 200 400 600 800 1000 0.95 1.00 1.05 1.10 1.15 TEMPERATURE (°C) CMOUT LOAD CURRENT (µA) INPUT COMMON-MODE VOLTAGE (V) 8 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs Pin Configuration M A X TOP VIEW 1 N.C. N.C. N.C. N.C. N.C. N.C. AVDD REFH REFIO REFL OGND OVDD 9 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. AVDD I.C. SHDN OUT1+ OUT1- 2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 7 IN1- IN1+ GND GND GND GND GND GND GND OGND OUT2+ OUT2- C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 IN2- IN2+ GND GND GND GND GND GND GND OGND OUT3+ OUT3- D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 IN3- IN3+ GND GND GND GND GND GND GND OGND OUT4+ OUT4- E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 IN4- IN4+ CMOUT GND GND GND AVDD GND GND OVDD CLKOUT+ CLKOUT- F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 IN5- IN5+ CMOUT GND GND GND AVDD GND GND OVDD FRAME+ FRAME- G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 IN6- IN6+ GND GND GND GND GND GND GND OGND OUT5+ OUT5- H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 IN7- IN7+ GND GND GND GND GND GND GND OGND OUT6+ OUT6- J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 IN8- IN8+ GND GND GND GND GND GND GND OGND OUT7+ OUT7- K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 N.C. N.C. N.C. N.C. N.C. N.C. AVDD CLKIN+ GND SDIO OUT8+ OUT8- L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 N.C. N.C. N.C. N.C. N.C. N.C. AVDD CLKIN- GND SCLK CS OVDD M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Pin Description PIN NAME FUNCTION ANALOG INPUTS C1 IN1- Channel 1 Negative (Inverting) Analog Input C2 IN1+ Channel 1 Positive (Noninverting) Analog Input D1 IN2- Channel 2 Negative (Inverting) Analog Input D2 IN2+ Channel 2 Positive (Noninverting) Analog Input E1 IN3- Channel 3 Negative (Inverting) Analog Input E2 IN3+ Channel 3 Positive (Noninverting) Analog Input F1 IN4- Channel 4 Negative (Inverting) Analog Input F2 IN4+ Channel 4 Positive (Noninverting) Analog Input 9 Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with Serial LVDS Outputs 7 Pin Description (continued) 2 5 PIN NAME FUNCTION 9 G1 IN5- Channel 5 Negative (Inverting) Analog Input 1 G2 IN5+ Channel 5 Positive (Noninverting) Analog Input X H1 IN6- Channel 6 Negative (Inverting) Analog Input A H2 IN6+ Channel 6 Positive (Noninverting) Analog Input J1 IN7- Channel 7 Negative (Inverting) Analog Input M J2 IN7+ Channel 7 Positive (Noninverting) Analog Input K1 IN8- Channel 8 Negative (Inverting) Analog Input K2 IN8+ Channel 8 Positive (Noninverting) Analog Input L8 CLKIN+ Clock Positive (Noninverting) Input Clock Negative (Inverting) Input. If CLKIN- is connected to ground, CLKIN+ is a single-ended, M8 CLKIN- logic-level clock input. Otherwise, CLKIN+ and CLKIN- are self-biased differential clock inputs. LVDS OUTPUTS B11 OUT1+ Channel 1 Positive (Noninverting) LVDS Digital Output B12 OUT1- Channel 1 Negative (Inverting) LVDS Digital Output C11 OUT2+ Channel 2 Positive (Noninverting) LVDS Digital Output C12 OUT2- Channel 2 Negative (Inverting) LVDS Digital Output D11 OUT3+ Channel 3 Positive (Noninverting) LVDS Digital Output D12 OUT3- Channel 3 Negative (Inverting) LVDS Digital Output E11 OUT4+ Channel 4 Positive (Noninverting) LVDS Digital Output E12 OUT4- Channel 4 Negative (Inverting) LVDS Digital Output F11 CLKOUT+ Positive (Noninverting) Serial LVDS Clock Output F12 CLKOUT- Negative (Inverting) Serial LVDS Clock Output Positive (Noninverting) Frame-Alignment LVDS Output. A rising edge on the differential FRAME G11 FRAME+ output aligns to a valid output data frame. Negative (Inverting) Frame-Alignment LVDS Output. A rising edge on the differential FRAME output G12 FRAME- aligns to a valid output data frame. H11 OUT5+ Channel 5 Positive (Noninverting) LVDS Digital Output H12 OUT5- Channel 5 Negative (Inverting) LVDS Digital Output J11 OUT6+ Channel 6 Positive (Noninverting) LVDS Digital Output J12 OUT6- Channel 6 Negative (Inverting) LVDS Digital Output K11 OUT7+ Channel 7 Positive (Noninverting) LVDS Digital Output K12 OUT7- Channel 7 Negative (Inverting) LVDS Digital Output L11 OUT8+ Channel 8 Positive (Noninverting) LVDS Digital Output L12 OUT8- Channel 8 Negative (Inverting) LVDS Digital Output 3-WIRE SERIAL PERIPHERAL INTERFACE (SPI) L10 SDIO SPI Data Input/Output M10 SCLK SPI Clock M11 CS SPI Chip Select 10

Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with - Maxim

Similar Ultra-Low-Power, Octal, 12-Bit, 50Msps, 1.8V ADC with - Maxim