Table Of ContentPCB Designer’s
SI Guide
A basic guide for SI and crosstalk for a PCB designer
Preface
What the heck is SI?
Why and what should I Simulate?
What is the strategy for SI Analysis?
Is crosstalk happens when you talk in the mobile?
What do you mean by transmission line?
Topology??? Are you kidding?
Delay?? How about a schedule change?
This is a collection of articles, which are found in web and other sources trying to answer your
questions. Hope it will be helpful
Table of Content
Basics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
1.2.1 Waveform Voltage Accuracy_______________________________________5
1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
2 Interconnections for High Speed Digital Circuits _______________________________10
2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic interfacing problems _______________________________10
2.3 IC Technology and Signal Integrity_____________________________________12
2.4 Speed and distance __________________________________________________14
2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
2.7 Review questions ___________________________________________________18
3 Interconnection Models____________________________________________________20
3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
3.3 Receiver model_____________________________________________________21
3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28
4 Transmission Line Models _________________________________________________31
4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss- less transmission lines ___________________________________________32
4.4 Critical Length _____________________________________________________34
4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
PCB Designer’s SI Guide Page 2 Venkata
5 Analysis techniques _______________________________________________________45
5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
5.3 Effects of termination resistance _______________________________________46
5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
5.7 Examples of results__________________________________________________54
5.8 Review questions ___________________________________________________55
6 Design guide for interconnection ____________________________________________57
6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67
7 Signal Integrity in Digital Circuits ___________________________________________70
7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
7.5 Examples__________________________________________________________76
7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81
8 Design Guide to Handle Crosstalk ___________________________________________85
8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk__________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
8.5 Review questions ___________________________________________________94
9 Ground Bounce and Switching Noise_________________________________________97
9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance__________________________________100
9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105
10 Design Guide for Ground & Power Distribution _____________________________107
10.1 Summary_________________________________________________________107
PCB Designer’s SI Guide Page 3 Venkata
10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
10.5 Clock distribution __________________________________________________115
10.6 Review Questions __________________________________________________118
11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices_____________________________________128
12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the
following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for
solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1 STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR
MIN/MAX VALUES ___________________________________________________135
12.3.3 STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES
136
12.3.4 STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH
CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS
APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES
ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8 STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM
137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND
USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
PCB Designer’s SI Guide Page 4 Venkata
Basics of SI
1.1 When Speed is important?
Speed is important when; the edge rate (rise or fall time) of a clock is fast enough that the signal can
change from one logic state to the other in the same or less time than it takes the signal to travel the
length of the wire or net.
1.1.1 Acceptable Voltage and timing values
Any voltage level within the values of the Vin Maximum to Vin Minimum is a valid logic signal.
Excursions outside these limits will cause logic malfunction. SI engineering involves; developing
design rules that insures all logic signals fall within the envelope for any allowed combination of
components, temperature and power supply voltage.
1.2 Signal Integrity
SI has 2 components that are interlinked; voltage accuracy of the waveform and timing of arrival of
switching edges at the input.
1.2.1 Waveform Voltage Accuracy
It is affected by impedance matches, ground bounce and coupling etc.
1.2.2 Timing
Is affected by propagation delay variations in ICs, travel time on wires, and variation in edge rates of
ICs.
1.3 Speed of currently used logic families
Logic type Typical edge speed Transition electrical Critical length in
(nSEC) length in FR-4 (inches) inches
STANDARD TTL 5.0 29.0 14.5
ASTTL 1.9 10.9 5.45
FTTL 1.2 6.9 3.45
10K ECL 2.5 14.4 7.2
BTL 1.0 5.8 3.9
CMOS/DS 1.5 9.0 4.5
LVDS 0.3 1.73 0.86
100K ECL 0.5 2.88 1.44
GA AS 106 0.3 1.73 0.86
GTL+(PENTPRO) 0.3 1.73 0.86
Overshoot and undershoot problems will start to occur at less than 1/3 of the Transition Electrical
Length (TEL) and may require series termination of transmission lines, as well as impedance control.
PCB Designer’s SI Guide Page 5 Venkata
1.3.1 Transition Electrical Length (TEL)
The length of transmission line represented by one rise or fall time. To obtain TEL, multiply rise or
fall time by velocity of travel of electromagnetic energy in the transmission line.
E.G. Rise time 1.5 nSEC, velocity 5.8 inches per nano second. So TEL = 1.5 X 5.8 = 8.7”
Velocity of travel of electromagnetic energy in transmission line = 5.8 inches/nSEC
1.3.2 Critical length
The length that two lines must run in parallel in order for backward cross talk to reach a maximum
or to saturate. This is approximately ½ of TEL.
1.3.3 What is Transmission Line?
• A transmission line is any pair of conductors that are used to move electromagnetic energy
from one place to another.
• In PCBs, this is typically a trace and one or more power planes
• Power lines are transmission lines
• Waveguides is a transmission lines
• TV Twin lead is a transmission line
• Co-axial cable is a transmission line
• Twisted pairs are transmission line.
All of the transmission line has characteristic impedance.
1.3.4 What is moving in a Transmission line?
• Rapidly changing electromagnetic field at or near the speed of light
• Typical EM Waves
• Radar waves, Light Waves, AM/FM Radio Wave, Pager Signals, EMI/RFI Energy, TV
Waves
EM waves do not depend on electrons for transmission, all move through vacuum at the speed of
light.
All are EM energy moving from place to place.
1.3.5 Power Plane Definition
• At transmission line speeds, all power planes in a PCB are ground planes, irrespective of
their DC names
• Any power plane can serve as the “ground” plane for any “fast” signal
• It is not necessary to route critical signals such as clocks over the plane called “DC’ ground
• Why is this so? By design, we short power planes together at ac frequencies. This shorting is
done using bypass capacitors of the PCB itself. If the power planes are not shorted at high
frequencies (meaning low power system impedance) there will be large amounts of noise on
the power supply rails (a common source of EMI in PCBs with small inter-plane
capacitance)
PCB Designer’s SI Guide Page 6 Venkata
1.3.6 The concept of Ground
The word Ground is used to describe a very wide variety of things in electronics.
Examples are chassis of unit, the plane half of transmission line, the reference terminal of an analog
system
By defining ground us: the point in an electronic system from which voltage measurements are
made. It is a reference point only. It has no meaning or function
Some grounds used in electronic circuits
• Chassis ground
•
• Logic Ground – this is the point where all measurements are made, no need to connect to
chassis
• Analog ground – this is commonly used to represent a point in a system that analog circuits
use to measure or compare analog signals. It can and must be connected to LOGIC
GROUND at some point
1.4 STRIPLINE circuit with Electromagnetic field
Magnetic lines of force (solid lines) encircle the signal conductor; electric lines of force (dotted lines)
connect the signal conductor to the reference plane
PCB Designer’s SI Guide Page 7 Venkata
1.5 RLC Transmission Line Model
This model assumes ground is plane of negligible inductance and resistance. The following
equations permit one to calculate the reactance of capacitors and inductors as a function of
frequency.
The equation for calculating the amount of capacitive reactance in an ac circuit is given by:
XC = 1 / (2πfC)
where:
XC = capacitive reactance in ohms
f = frequency in hertz
C = capacitance in farads
The equation for calculating the amount of inductive reactance in an ac circuit is given
by:
XL = 2πfL
Where:
XL = inductive reactance ohms (Ω)
f = frequency in hertz (Hz)
L = inductance in henries (H)
1.5.1 What is Impedance?
• Impedance is the resistance to the flow of energy in a transmission line
• At low frequencies, it is primarily DC resistance of the bulk copper and is relatively small in
PCB traces
• At high frequencies it is primarily reactive and substantially higher than the DC or low
frequency value
• Reactance is both capacitive and inductive
1.5.2 A Practical impedance equation for microstrip
PCB Designer’s SI Guide Page 8 Venkata
79 5.98H
Z = ln
o
e
r +1.41 0.8W +T
Zo = Trace impedance in OHMS
Er = Relative Dielectric constant
H = Height of trace above plane
T = Trace Thickness
Valid for 5<w<15 mils
1.5.3 What is relative dielectric constant Er?
• Relative dielectric constant, Er, is a measure of the affect an insulator has on capacitance of a pair
of conductors as compared to same conductor pair in a vacuum.
• The dielectric constant in vacuum is 1.
An equation for calculating Er using velocity measure with a TDR (time domain reflection)
c
e = Where c = speed of light; v = measure propagation velocity
r
v
PCB Designer’s SI Guide Page 9 Venkata
2 Interconnections for High Speed
Digital Circuits
2.1.1 Summary
The first lesson answers the following questions:
• Which kinds of systems are addressed?
• What does "dynamic interfacing" mean?
• Which kinds of signals are analyzed here?
• Which are the relevant static parameters of digital logic circuits?
2.2 Examples of dynamic interfacing problems
1) Spikes and temporary faults appear at the output of a combinatorial circuit. The
reason is that the change of logic state is sensed with different delays by a logic
circuit connected to the same signal. This may cause transient combinations of logic
states, which were not taken into account in the design process.
2) Figure 1.1 shows two microprocessors driven by the same clock signal. That means they should
run synchronously, without problems related with marginal timing, such as metastability. In the real
circuit, for some combinations of temperature and supply voltage, the system exhibits random errors
for microprocessor 2. Swapping the devices has no effect; therefore the problem is related with the
socket, not with the device.
Figure 1.1 Clock distributions to a couple of microprocessors.
The random errors are caused by synchronization problems (metastability) in the information
exchange between the two microprocessors. The solution is a redesign of the clock distribution
circuit as in Figure 1.2, taking into account transmission line effects. This can guarantee the timing
margins for the synchronous circuits of the two microprocessors.
PCB Designer’s SI Guide Page 10 Venkata
