Table Of ContentAbout the Author
Nikrouz Faroughi has a BS in computer engineering, MS in
computer science, MS in electrical engineering, and PhD in electrical
engineering with a specialization in computer engineering from
Michigan State University. He has worked as a systems analyst and
currently is a professor and graduate coordinator in the Computer
Science Department and a faculty member in the Computer
Engineering Program at California State University, Sacramento. As
a consultant, he has worked and also served as a technical manager
at Intel Corporation.
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Contents
Preface
Acknowledgment
1 Introduction
1.1 Introduction
1.1.1 Data Representation
1.1.2 Data Path
1.1.3 Computer Systems
1.1.4 Embedded Systems
1.2 Logic Design
1.2.1 Circuit Minimization
1.2.2 Implementation
1.2.3 Types of Circuits
1.2.4 Computer-Aided Design Tools
1.3 Computer Organization
1.4 Computer Architecture
1.4.1 Pipelining
1.4.2 Parallelism
1.5 Computer Security
References
Exercises
2 Combinational Circuits: Small Designs
2.1 Introduction
2.1.1 Signal Naming Standards
2.2 Logic Expressions
2.2.1 Sum of Product Expression
2.2.2 Product of Sum Expression
2.3 Canonical Expression
2.3.1 Min-Terms
2.3.2 Max-Terms
2.4 Logic Minimization
2.4.1 Karnaugh Map
2.4.2 K-Map Minimization
2.5 Logic Minimization Algorithm
2.5.1 Minimization Software
2.6 Circuit Timing Diagram
2.6.1 Signal Propagation Delay
2.6.2 Fan-In and Fan-Out
2.7 Other Gates
2.7.1 Buffer
2.7.2 Open Collector Buffer
2.7.3 Tri-State Buffer
2.8 Design Examples
2.8.1 Full Adder
2.8.2 Multiplexer
2.8.3 Decoder
2.8.4 Encoder
2.9 Implementation
2.9.1 Programmable Logic Devices
2.9.2 Design Flow
2.10 Hardware Description Languages
2.10.1 Structural Model
2.10.2 Propagation Delay Simulation
2.10.3 Behavioral Modeling
2.10.4 Synthesis and Simulation
References
Exercises
3 Combinational Circuits: Large Designs
3.1 Introduction
3.1.1 Top-Down Design Methodology
3.2 Arithmetic Functions
3.3 Adder
3.3.1 Carry Propagate Adder
3.3.2 Carry Look-Ahead Adder
3.4 Subtractor
3.5 2’s Complement Adder/Subtractor
3.6 Arithmetic Logic Unit
3.6.1 Design Partitioning: Bit-Parallel
3.6.2 Design Partitioning: Bit-Serial
3.7 Design Examples
3.7.1 Multiplier
3.7.2 Divider
3.8 Real Number Arithmetic
3.8.1 Floating-Point Standards
3.8.2 Floating-Point Data Space
3.8.3 Floating-Point Arithmetic
3.8.4 Floating-Point Unit
References
Exercises
4 Sequential Circuits: Core Modules
4.1 Introduction
4.2 SR Latch
4.2.1 Clocked SR Latch
4.3 D-Latch
4.4 Disadvantage of Latches
4.5 D Flip-Flop
4.5.1 Alternative Circuit
4.5.2 Operating Conventions
4.5.3 Setup and Hold Times
4.6 Clock Frequency Estimation without Clock Skew
4.7 Flip-Flop with Enable
4.8 Other Flip-Flops
4.9 Hardware Description Language Models
References
Exercises
5 Sequential Circuits: Small Designs
5.1 Introduction
5.2 Introduction to FSM: Register Design
5.2.1 Register Model
5.2.2 Multifunction Registers
5.3 Finite State Machine Design
5.3.1 Binary Encoded States
5.3.2 One-Hot Encoded States
5.4 Counters
5.5 Fault-Tolerant Finite State Machine
5.5.1 Hamming Coding Scheme
5.6 Sequential Circuit Timing
5.6.1 Clock Frequency Estimation with Clock Skew
5.6.2 Asynchronous Interface
5.7 Hardware Description Language Models
5.7.1 Synthesis and Simulation
References
Exercises
6 Sequential Circuits: Large Designs
6.1 Introduction
6.1.1 Register Transfer Notation
