Free Range VHDL

2013·2.3 MB·English

by  Fabrizio Tappero and Bryan Mealy

Free Range VHDL
Bryan Mealy, Fabrizio Tappero
Free Range VHDL
Copyright '2013 B. Mealy, F. Tappero
Release: 1.17
Date: 21 June 2013
Book size: 160 mm by 240 mm
Pages: approx. 190
The electronic version of this book can be downloaded free of charge from:
http://www.freerangefactory.org
The authors have taken great care in the preparation of this book, but make no ex-
pressed or implied warranty of any kind and assume no responsibility for errors or
omissions. No liability is assumed for incidental or consequential damages in connec-
tionwithorarisingoutoftheuseoftheinformationorprogramscontainedinthisbook.
This book is licensed under the Creative Commons Attribution-ShareAlike Unported
License, which permits unrestricted use, distribution, adaptation and reproduction in
any medium, provided theoriginal work isproperly cited.If you build upon thiswork,
you may distribute the resulting work only under the same, similar or a compatible
license. To view a copy of this license, visit:
http://creativecommons.org/licenses/by-sa/3.0/
Feedback and Contribution
We are more than happy to consider your contribution in improving, extending or
correcting any part of this book. For any communication or feedback that you might
haveaboutthecontentofthisbookyoucancontacttheauthorsatthefollowingaddress:
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Cover and Artwork by Robert Ash.
To everyone who helped

Table of Contents
Acknowledgments ii
Purpose of this book 1
1 Introduction To VHDL 5
1.1 Golden Rules of VHDL 8
1.2 Tools Needed for VHDL Development 8
2 VHDL Invariants 11
2.1 Case Sensitivity 11
2.2 White Space 11
2.3 Comments 12
2.4 Parentheses 12
2.5 VHDL Statements 13
2.6 if, case and loop Statements 13
2.7 Identifiers 14
2.8 Reserved Words 15
2.9 VHDL Coding Style 15
3 VHDL Design Units 17
3.1 Entity 18
3.2 VHDL Standard Libraries 22
ii
3.3 Architecture 23
3.4 Signal and Variable Assignments 23
3.5 Summary 25
3.6 Exercises 26
4 VHDL Programming Paradigm 29
4.1 Concurrent Statements 30
4.2 Signal Assignment Operator “<=” 33
4.3 Concurrent Signal Assignment Statements 34
4.4 Conditional Signal Assignment when 38
4.5 Selected Signal Assignment with select 42
4.6 Process Statement 47
4.7 Summary 47
4.8 Exercises 48
5 Standard Models in VHDL Architectures 51
5.1 Data-flow Style Architecture 52
5.2 Behavioral Style Architecture 53
5.3 Process Statement 53
5.4 Sequential Statements 55
5.4.1 Signal Assignment Statement 57
5.4.2 if Statement 57
5.4.3 case Statement 62
5.5 Caveats Regarding Sequential Statements 66
5.6 Summary 68
5.7 Exercises: Behavioral Modeling 68
6 VHDL Operators 71
6.1 Logical Operators 72
6.2 Relational Operators 72
6.3 Shift Operator 72
6.4 Other Operators 73
6.5 Concatenation Operator 74
6.6 Modulus and Remainder Operators 74
6.7 Review of Almost Everything Up to Now 75
iii
6.8 Using VHDL for Sequential Circuits 76
6.9 Simple Storage Elements Using VHDL 77
6.10 Inducing Memory: Data-flow vs. Behavioral Modeling 84
6.11 Important Points 85
6.12 Exercises: Basic Memory Elements 86
7 Finite State Machine Design Using VHDL 89
7.1 VHDL Behavioral Representation of FSMs 92
7.2 One-Hot Encoding for FSMs 101
7.3 Important Points 106
7.4 Exercises: Behavioral Modeling of FSMs 107
8 Structural Modeling In VHDL 117
8.1 VHDL Modularity with Components 119
8.2 Generic Map 127
8.3 Important Points 128
8.4 Exercises: Structural Modeling 129
9 Registers and Register Transfer Level 131
9.1 Important Points 138
9.2 Exercises: Register Transfer Level Circuits 138
10 Data Objects 141
10.1 Types of Data Objects 141
10.2 Data Object Declarations 142
10.3 Variables and Assignment Operator “:=” 143
10.4 Signals vs. Variables 143
10.5 Standard Data Types 145
10.6 User-Defined Types 145
10.7 Commonly Used Types 146
10.8 Integer Types 146
10.9 signed and unsigned Types 148
10.10 std logic Types 149
10.11 Important Points 152
iv
11 Looping Constructs 153
11.1 for and while Loops 153
11.1.1 for Loops 154
11.1.2 while Loops 156
11.1.3 Loop Control: next and exit Statements 156
12 Standard Digital Circuits in VHDL 159
12.1 RET D Flip-flop - Behavioral Model 160
12.2 FET D Flip-flop with Active-low Asynchronous Preset -
Behavioral Model 160
12.3 8-Bit Register with Load Enable - Behavioral Model 161
12.4 Synchronous Up/Down Counter - Behavioral Model 161
12.5 ShiftRegisterwithSynchronousParallelLoad-Behavioral
Model 162
12.6 8-Bit Comparator - Behavioral Model 163
12.7 BCD to 7-Segment Decoder - Data-Flow Model 163
12.8 4:1 Multiplexer - Behavioral Model 164
12.9 4:1 Multiplexer - Data-Flow Model 164
12.10 Decoder 165
Appendix A VHDL Reserved Words 167
Appendix B Standard VHDL Packages 169
B.1 IEEE Standard Libraries 171
B.2 Non-standard Libraries 172
Appendix C VHDL Reference Cards 173
Appendix D Contributors to This Book 179